1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/clk-provider.h>
9 #include <dt-bindings/clock/imx27-clock.h>
41 	"ahb", "ipg", "per1_div", "per2_div",
43 	"nfc_div", "mshc_div", "vpu_div", "60m",
81 		clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2);  in _mx27_clocks_init()
82 		clk[IMX27_CLK_IPG] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);  in _mx27_clocks_init()
84 		clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4);  in _mx27_clocks_init()
85 		clk[IMX27_CLK_IPG] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1);  in _mx27_clocks_init()
88 	clk[IMX27_CLK_MSHC_DIV] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6);  in _mx27_clocks_init()
89 	clk[IMX27_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4);  in _mx27_clocks_init()
151 	clk[IMX27_CLK_USB_AHB_GATE] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11);  in _mx27_clocks_init()
152 	clk[IMX27_CLK_SLCDC_AHB_GATE] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12);  in _mx27_clocks_init()
153 	clk[IMX27_CLK_SAHARA_AHB_GATE] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13);  in _mx27_clocks_init()
154 	clk[IMX27_CLK_RTIC_AHB_GATE] = imx_clk_gate("rtic_ahb_gate", "ahb", CCM_PCCR1, 14);  in _mx27_clocks_init()
155 	clk[IMX27_CLK_LCDC_AHB_GATE] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15);  in _mx27_clocks_init()
156 	clk[IMX27_CLK_VPU_AHB_GATE] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16);  in _mx27_clocks_init()
157 	clk[IMX27_CLK_FEC_AHB_GATE] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17);  in _mx27_clocks_init()
158 	clk[IMX27_CLK_EMMA_AHB_GATE] = imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18);  in _mx27_clocks_init()
159 	clk[IMX27_CLK_EMI_AHB_GATE] = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19);  in _mx27_clocks_init()
160 	clk[IMX27_CLK_DMA_AHB_GATE] = imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20);  in _mx27_clocks_init()
161 	clk[IMX27_CLK_CSI_AHB_GATE] = imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21);  in _mx27_clocks_init()
162 	clk[IMX27_CLK_BROM_AHB_GATE] = imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22);  in _mx27_clocks_init()
163 	clk[IMX27_CLK_ATA_AHB_GATE] = imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23);  in _mx27_clocks_init()
189 	for_each_compatible_node(refnp, NULL, "fixed-clock") {  in mx27_clocks_init_dt()
190 		if (!of_device_is_compatible(refnp, "fsl,imx-osc26m"))  in mx27_clocks_init_dt()
193 		if (!of_property_read_u32(refnp, "clock-frequency", &fref)) {  in mx27_clocks_init_dt()
207 CLK_OF_DECLARE(imx27_ccm, "fsl,imx27-ccm", mx27_clocks_init_dt);