Lines Matching +full:m +full:- +full:ahb
1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/clock/imx6sx-clock.h>
10 #include <linux/clk-provider.h>
37 static const char *pcie_axi_sels[] = { "axi", "ahb", };
61 "lcdif1_pix", "ahb", "ipg", "perclk", "ckil", "pll4_audio_div",
138 clk_hw_data->num = IMX6SX_CLK_CLK_END; in imx6sx_clocks_init()
139 hws = clk_hw_data->hws; in imx6sx_clocks_init()
154 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop"); in imx6sx_clocks_init()
185 clk_set_parent(hws[IMX6SX_PLL1_BYPASS]->clk, hws[IMX6SX_CLK_PLL1]->clk); in imx6sx_clocks_init()
186 clk_set_parent(hws[IMX6SX_PLL2_BYPASS]->clk, hws[IMX6SX_CLK_PLL2]->clk); in imx6sx_clocks_init()
187 clk_set_parent(hws[IMX6SX_PLL3_BYPASS]->clk, hws[IMX6SX_CLK_PLL3]->clk); in imx6sx_clocks_init()
188 clk_set_parent(hws[IMX6SX_PLL4_BYPASS]->clk, hws[IMX6SX_CLK_PLL4]->clk); in imx6sx_clocks_init()
189 clk_set_parent(hws[IMX6SX_PLL5_BYPASS]->clk, hws[IMX6SX_CLK_PLL5]->clk); in imx6sx_clocks_init()
190 clk_set_parent(hws[IMX6SX_PLL6_BYPASS]->clk, hws[IMX6SX_CLK_PLL6]->clk); in imx6sx_clocks_init()
191 clk_set_parent(hws[IMX6SX_PLL7_BYPASS]->clk, hws[IMX6SX_CLK_PLL7]->clk); in imx6sx_clocks_init()
202 * Bit 20 is the reserved and read-only bit, we do this only for: in imx6sx_clocks_init()
203 * - Do nothing for usbphy clk_enable/disable in imx6sx_clocks_init()
204 * - Keep refcount when do usbphy clk_enable/disable, in that case, in imx6sx_clocks_init()
323 …hws[IMX6SX_CLK_IPG] = imx_clk_hw_divider("ipg", "ahb", bas… in imx6sx_clocks_init()
372 …hws[IMX6SX_CLK_AHB] = imx_clk_hw_busy_divider("ahb", "periph", base + 0x14… in imx6sx_clocks_init()
378 …hws[IMX6SX_CLK_AIPS_TZ1] = imx_clk_hw_gate2_flags("aips_tz1", "ahb", base + 0x68, 0, CLK_IS_CR… in imx6sx_clocks_init()
379 …hws[IMX6SX_CLK_AIPS_TZ2] = imx_clk_hw_gate2_flags("aips_tz2", "ahb", base + 0x68, 2, CLK_IS_CR… in imx6sx_clocks_init()
381 …hws[IMX6SX_CLK_ASRC_MEM] = imx_clk_hw_gate2_shared("asrc_mem", "ahb", base + 0x68,… in imx6sx_clocks_init()
382 …hws[IMX6SX_CLK_ASRC_IPG] = imx_clk_hw_gate2_shared("asrc_ipg", "ahb", base + 0x68,… in imx6sx_clocks_init()
383 …hws[IMX6SX_CLK_CAAM_MEM] = imx_clk_hw_gate2("caam_mem", "ahb", base + 0x68,… in imx6sx_clocks_init()
384 …hws[IMX6SX_CLK_CAAM_ACLK] = imx_clk_hw_gate2("caam_aclk", "ahb", base + 0x68,… in imx6sx_clocks_init()
392 …hws[IMX6SX_CLK_AIPS_TZ3] = imx_clk_hw_gate2_flags("aips_tz3", "ahb", base + 0x68, 30, CLK_IS_C… in imx6sx_clocks_init()
403 …hws[IMX6SX_CLK_ESAI_IPG] = imx_clk_hw_gate2_shared("esai_ipg", "ahb", base + 0x6c,… in imx6sx_clocks_init()
404 …hws[IMX6SX_CLK_ESAI_MEM] = imx_clk_hw_gate2_shared("esai_mem", "ahb", base + 0x6c,… in imx6sx_clocks_init()
409 …hws[IMX6SX_CLK_OCRAM_S] = imx_clk_hw_gate2("ocram_s", "ahb", base + 0x6c,… in imx6sx_clocks_init()
419 …hws[IMX6SX_CLK_IPMUX1] = imx_clk_hw_gate2_flags("ipmux1", "ahb", base + 0x70, 16, CLK_IS_CRI… in imx6sx_clocks_init()
420 …hws[IMX6SX_CLK_IPMUX2] = imx_clk_hw_gate2_flags("ipmux2", "ahb", base + 0x70, 18, CLK_IS_CRI… in imx6sx_clocks_init()
421 …hws[IMX6SX_CLK_IPMUX3] = imx_clk_hw_gate2_flags("ipmux3", "ahb", base + 0x70, 20, CLK_IS_CRI… in imx6sx_clocks_init()
435 …hws[IMX6SX_CLK_MLB] = imx_clk_hw_gate2("mlb", "ahb", base + 0x74,… in imx6sx_clocks_init()
445 …hws[IMX6SX_CLK_PER2_MAIN] = imx_clk_hw_gate2_flags("per2_main", "ahb", base + 0x78, 14, CLK_IS_… in imx6sx_clocks_init()
456 …hws[IMX6SX_CLK_ROM] = imx_clk_hw_gate2_flags("rom", "ahb", base + 0x7c, 0, CLK_IS_CRITICA… in imx6sx_clocks_init()
457 …hws[IMX6SX_CLK_SDMA] = imx_clk_hw_gate2("sdma", "ahb", base + 0x7c,… in imx6sx_clocks_init()
501 clk_prepare_enable(hws[IMX6SX_CLK_USBPHY1_GATE]->clk); in imx6sx_clocks_init()
502 clk_prepare_enable(hws[IMX6SX_CLK_USBPHY2_GATE]->clk); in imx6sx_clocks_init()
506 clk_set_parent(hws[IMX6SX_CLK_EIM_SLOW_SEL]->clk, hws[IMX6SX_CLK_PLL2_PFD2]->clk); in imx6sx_clocks_init()
507 clk_set_rate(hws[IMX6SX_CLK_EIM_SLOW]->clk, 132000000); in imx6sx_clocks_init()
510 clk_set_parent(hws[IMX6SX_CLK_LCDIF1_PRE_SEL]->clk, hws[IMX6SX_CLK_PLL5_VIDEO_DIV]->clk); in imx6sx_clocks_init()
511 clk_set_parent(hws[IMX6SX_CLK_LCDIF1_SEL]->clk, hws[IMX6SX_CLK_LCDIF1_PODF]->clk); in imx6sx_clocks_init()
514 if (clk_set_parent(hws[IMX6SX_CLK_LVDS1_SEL]->clk, hws[IMX6SX_CLK_PCIE_REF_125M]->clk)) in imx6sx_clocks_init()
518 * Init enet system AHB clock, set to 200MHz in imx6sx_clocks_init()
519 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB in imx6sx_clocks_init()
521 clk_set_parent(hws[IMX6SX_CLK_ENET_PRE_SEL]->clk, hws[IMX6SX_CLK_PLL2_PFD2]->clk); in imx6sx_clocks_init()
522 clk_set_parent(hws[IMX6SX_CLK_ENET_SEL]->clk, hws[IMX6SX_CLK_ENET_PODF]->clk); in imx6sx_clocks_init()
523 clk_set_rate(hws[IMX6SX_CLK_ENET_PODF]->clk, 200000000); in imx6sx_clocks_init()
524 clk_set_rate(hws[IMX6SX_CLK_ENET_REF]->clk, 125000000); in imx6sx_clocks_init()
525 clk_set_rate(hws[IMX6SX_CLK_ENET2_REF]->clk, 125000000); in imx6sx_clocks_init()
528 clk_set_rate(hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk, 393216000); in imx6sx_clocks_init()
530 clk_set_parent(hws[IMX6SX_CLK_SPDIF_SEL]->clk, hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk); in imx6sx_clocks_init()
531 clk_set_rate(hws[IMX6SX_CLK_SPDIF_PODF]->clk, 98304000); in imx6sx_clocks_init()
533 clk_set_parent(hws[IMX6SX_CLK_AUDIO_SEL]->clk, hws[IMX6SX_CLK_PLL3_USB_OTG]->clk); in imx6sx_clocks_init()
534 clk_set_rate(hws[IMX6SX_CLK_AUDIO_PODF]->clk, 24000000); in imx6sx_clocks_init()
536 clk_set_parent(hws[IMX6SX_CLK_SSI1_SEL]->clk, hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk); in imx6sx_clocks_init()
537 clk_set_parent(hws[IMX6SX_CLK_SSI2_SEL]->clk, hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk); in imx6sx_clocks_init()
538 clk_set_parent(hws[IMX6SX_CLK_SSI3_SEL]->clk, hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk); in imx6sx_clocks_init()
539 clk_set_rate(hws[IMX6SX_CLK_SSI1_PODF]->clk, 24576000); in imx6sx_clocks_init()
540 clk_set_rate(hws[IMX6SX_CLK_SSI2_PODF]->clk, 24576000); in imx6sx_clocks_init()
541 clk_set_rate(hws[IMX6SX_CLK_SSI3_PODF]->clk, 24576000); in imx6sx_clocks_init()
543 clk_set_parent(hws[IMX6SX_CLK_ESAI_SEL]->clk, hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk); in imx6sx_clocks_init()
544 clk_set_rate(hws[IMX6SX_CLK_ESAI_PODF]->clk, 24576000); in imx6sx_clocks_init()
547 clk_set_parent(hws[IMX6SX_CLK_VID_SEL]->clk, hws[IMX6SX_CLK_PLL3_USB_OTG]->clk); in imx6sx_clocks_init()
550 clk_set_parent(hws[IMX6SX_CLK_CAN_SEL]->clk, hws[IMX6SX_CLK_PLL3_60M]->clk); in imx6sx_clocks_init()
552 /* Update gpu clock from default 528M to 720M */ in imx6sx_clocks_init()
553 clk_set_parent(hws[IMX6SX_CLK_GPU_CORE_SEL]->clk, hws[IMX6SX_CLK_PLL3_PFD0]->clk); in imx6sx_clocks_init()
554 clk_set_parent(hws[IMX6SX_CLK_GPU_AXI_SEL]->clk, hws[IMX6SX_CLK_PLL3_PFD0]->clk); in imx6sx_clocks_init()
556 clk_set_parent(hws[IMX6SX_CLK_QSPI1_SEL]->clk, hws[IMX6SX_CLK_PLL2_BUS]->clk); in imx6sx_clocks_init()
557 clk_set_parent(hws[IMX6SX_CLK_QSPI2_SEL]->clk, hws[IMX6SX_CLK_PLL2_BUS]->clk); in imx6sx_clocks_init()
562 uart_clks[i] = &hws[index]->clk; in imx6sx_clocks_init()
567 CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init);