| /Linux-v5.10/arch/arm/boot/dts/ |
| D | axm5516-cpus.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * arch/arm/boot/dts/axm5516-cpus.dtsi
10 #address-cells = <1>;
11 #size-cells = <0>;
13 cpu-map {
16 cpu = <&CPU0>;
19 cpu = <&CPU1>;
22 cpu = <&CPU2>;
25 cpu = <&CPU3>;
30 cpu = <&CPU4>;
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| D | bcm2837.dtsi | 2 #include "bcm2835-common.dtsi"
3 #include "bcm2835-rpi-common.dtsi"
11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
14 compatible = "brcm,bcm2836-l1-intc";
16 interrupt-controller;
17 #interrupt-cells = <2>;
18 interrupt-parent = <&local_intc>;
22 arm-pmu {
23 compatible = "arm,cortex-a53-pmu";
24 interrupt-parent = <&local_intc>;
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| D | stih418.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "stih418-clock.dtsi"
7 #include "stih407-family.dtsi"
8 #include "stih410-pinctrl.dtsi"
11 #address-cells = <1>;
12 #size-cells = <0>;
13 cpu@2 {
14 device_type = "cpu";
15 compatible = "arm,cortex-a9";
17 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
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| /Linux-v5.10/Documentation/devicetree/bindings/arm/ |
| D | cpus.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15 defining properties for every cpu.
17 Bindings for CPU nodes follow the Devicetree Specification, available from:
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
34 cpus and cpu node bindings definition
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| /Linux-v5.10/drivers/soc/renesas/ |
| D | r9a06g032-smp.c | 1 // SPDX-License-Identifier: GPL-2.0
8 * Derived from actions,s500-smp
17 * The second CPU is parked in ROM at boot time. It requires waking it after
20 * So the default value of the "cpu-release-addr" corresponds to BOOTADDR...
25 * So for NONSEC mode, the bootloader re-parks the second CPU into a pen
26 * in SRAM, and changes the "cpu-release-addr" of linux's DT to a SRAM address,
35 r9a06g032_smp_boot_secondary(unsigned int cpu, in r9a06g032_smp_boot_secondary() argument
39 return -ENODEV; in r9a06g032_smp_boot_secondary()
44 arch_send_wakeup_ipi_mask(cpumask_of(cpu)); in r9a06g032_smp_boot_secondary()
54 int ret = -EINVAL, dns; in r9a06g032_smp_prepare_cpus()
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| /Linux-v5.10/Documentation/devicetree/bindings/cpu/ |
| D | cpu-topology.txt | 2 CPU topology binding description
6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
20 For instance in a system where CPUs support SMT, "cpu" nodes represent all
22 In systems where SMT is not supported "cpu" nodes represent all cores present
25 CPU topology bindings allow one to associate cpu nodes with hierarchical groups
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| /Linux-v5.10/arch/arm64/boot/dts/arm/ |
| D | foundation-v8-spin-table.dtsi | 8 enable-method = "spin-table";
9 cpu-release-addr = <0x0 0x8000fff8>;
13 enable-method = "spin-table";
14 cpu-release-addr = <0x0 0x8000fff8>;
18 enable-method = "spin-table";
19 cpu-release-addr = <0x0 0x8000fff8>;
23 enable-method = "spin-table";
24 cpu-release-addr = <0x0 0x8000fff8>;
|
| D | rtsm_ve-aemv8a.dts | 1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
36 #address-cells = <2>;
37 #size-cells = <0>;
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| /Linux-v5.10/arch/arm64/boot/dts/toshiba/ |
| D | tmpv7708.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * (C) Copyright 2018 - 2020, Toshiba Corporation.
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 /memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */
17 #address-cells = <2>;
18 #size-cells = <2>;
21 #address-cells = <1>;
22 #size-cells = <0>;
24 cpu-map {
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| /Linux-v5.10/arch/arm64/kernel/ |
| D | smp_spin_table.c | 1 // SPDX-License-Identifier: GPL-2.0-only
43 static int smp_spin_table_cpu_init(unsigned int cpu) in smp_spin_table_cpu_init() argument
48 dn = of_get_cpu_node(cpu, NULL); in smp_spin_table_cpu_init()
50 return -ENODEV; in smp_spin_table_cpu_init()
53 * Determine the address from which the CPU is polling. in smp_spin_table_cpu_init()
55 ret = of_property_read_u64(dn, "cpu-release-addr", in smp_spin_table_cpu_init()
56 &cpu_release_addr[cpu]); in smp_spin_table_cpu_init()
58 pr_err("CPU %d: missing or invalid cpu-release-addr property\n", in smp_spin_table_cpu_init()
59 cpu); in smp_spin_table_cpu_init()
66 static int smp_spin_table_cpu_prepare(unsigned int cpu) in smp_spin_table_cpu_prepare() argument
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| /Linux-v5.10/arch/arm64/boot/dts/freescale/ |
| D | s32v234.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
4 * Copyright 2016-2018 NXP
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
23 #address-cells = <2>;
24 #size-cells = <0>;
26 cpu0: cpu@0 {
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| /Linux-v5.10/arch/arm/mach-sti/ |
| D | platsmp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-sti/platsmp.c
8 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
30 static int sti_boot_secondary(unsigned int cpu, struct task_struct *idle) in sti_boot_secondary() argument
35 * Secondary CPU is initialised and started by a U-BOOTROM firmware. in sti_boot_secondary()
36 * Secondary CPU is spinning and waiting for a write at cpu_strt_ptr. in sti_boot_secondary()
54 int cpu; in sti_smp_prepare_cpus() local
56 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); in sti_smp_prepare_cpus()
67 for_each_possible_cpu(cpu) { in sti_smp_prepare_cpus()
69 np = of_get_cpu_node(cpu, NULL); in sti_smp_prepare_cpus()
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| /Linux-v5.10/arch/powerpc/boot/dts/ |
| D | iss4xx-mpic.dts | 15 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
22 model = "ibm,iss-4xx";
23 compatible = "ibm,iss-4xx";
24 dcr-parent = <&{/cpus/cpu@0}>;
31 #address-cells = <1>;
32 #size-cells = <0>;
34 cpu@0 {
35 device_type = "cpu";
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| /Linux-v5.10/Documentation/translations/zh_CN/arm64/ |
| D | booting.txt | 12 ---------------------------------------------------------------------
26 ---------------------------------------------------------------------
36 AArch64 异常模型由多个异常级（EL0 - EL3）组成，对于 EL0 和 EL1 异常级
41 这个术语来定义在将控制权交给 Linux 内核前 CPU 上执行的所有软件。
54 -----------------
65 ---------------
77 -------------
87 -------------
107 - 自 v3.17 起，除非另有说明，所有域都是小端模式。
109 - code0/code1 负责跳转到 stext.
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| /Linux-v5.10/arch/sh/kernel/cpu/sh2/ |
| D | smp-j2.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2016 Smart Energy Instruments, Inc.
23 unsigned cpu = hard_smp_processor_id(); in j2_ipi_interrupt_handler() local
24 volatile unsigned *pmsg = &per_cpu(j2_ipi_messages, cpu); in j2_ipi_interrupt_handler()
48 np = of_find_compatible_node(NULL, NULL, "jcore,ipi-controller"); in j2_prepare_cpus()
57 np = of_find_compatible_node(NULL, NULL, "jcore,cpuid-mmio"); in j2_prepare_cpus()
79 static void j2_start_cpu(unsigned int cpu, unsigned long entry_point) in j2_start_cpu() argument
83 void __iomem *release, *initpc; in j2_start_cpu() local
85 if (!cpu) return; in j2_start_cpu()
87 np = of_get_cpu_node(cpu, NULL); in j2_start_cpu()
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| /Linux-v5.10/arch/powerpc/kernel/ |
| D | mce.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
69 mce->error_type = mce_err->error_type; in mce_set_error_info()
70 switch (mce_err->error_type) { in mce_set_error_info()
72 mce->u.ue_error.ue_error_type = mce_err->u.ue_error_type; in mce_set_error_info()
75 mce->u.slb_error.slb_error_type = mce_err->u.slb_error_type; in mce_set_error_info()
78 mce->u.erat_error.erat_error_type = mce_err->u.erat_error_type; in mce_set_error_info()
81 mce->u.tlb_error.tlb_error_type = mce_err->u.tlb_error_type; in mce_set_error_info()
84 mce->u.user_error.user_error_type = mce_err->u.user_error_type; in mce_set_error_info()
87 mce->u.ra_error.ra_error_type = mce_err->u.ra_error_type; in mce_set_error_info()
90 mce->u.link_error.link_error_type = mce_err->u.link_error_type; in mce_set_error_info()
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| /Linux-v5.10/arch/arm64/boot/dts/apm/ |
| D | apm-shadowcat.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
9 compatible = "apm,xgene-shadowcat";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
18 cpu@0 {
19 device_type = "cpu";
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| /Linux-v5.10/drivers/base/ |
| D | devres.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/base/devres.c - device resource management
20 dr_release_t release; member
32 * the alignment of a 64-bit integer.
43 /* -- 8 pointers */
53 node->name = name; in set_node_dbginfo()
54 node->size = size; in set_node_dbginfo()
62 op, node, node->name, (unsigned long)node->size); in devres_log()
70 * Release functions for devres group. These callbacks are used only
85 if (node->release == &group_open_release) in node_to_group()
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| D | cpu.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * CPU subsystem support
10 #include <linux/cpu.h>
38 static void change_cpu_under_node(struct cpu *cpu, in change_cpu_under_node() argument
41 int cpuid = cpu->dev.id; in change_cpu_under_node()
44 cpu->node_id = to_nid; in change_cpu_under_node()
49 struct cpu *cpu = container_of(dev, struct cpu, dev); in cpu_subsys_online() local
50 int cpuid = dev->id; in cpu_subsys_online()
56 return -ENODEV; in cpu_subsys_online()
60 * When hot adding memory to memoryless node and enabling a cpu in cpu_subsys_online()
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| /Linux-v5.10/arch/powerpc/platforms/44x/ |
| D | iss4xx.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Copyright 2002-2005 MontaVista Software Inc.
12 * Copyright (c) 2003-2005 Zultys Technologies
54 for_each_node_with_property(np, "interrupt-controller") { in iss4xx_init_irq()
66 } else if (of_device_is_compatible(np, "chrp,open-pic")) { in iss4xx_init_irq()
68 * device-tree, just pass 0 to all arguments in iss4xx_init_irq()
80 static void smp_iss4xx_setup_cpu(int cpu) in smp_iss4xx_setup_cpu() argument
85 static int smp_iss4xx_kick_cpu(int cpu) in smp_iss4xx_kick_cpu() argument
87 struct device_node *cpunode = of_get_cpu_node(cpu, NULL); in smp_iss4xx_kick_cpu()
94 /* Assume spin table. We could test for the enable-method in in smp_iss4xx_kick_cpu()
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| /Linux-v5.10/arch/arc/kernel/ |
| D | setup.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
15 #include <linux/cpu.h>
31 #include <asm/dsp-impl.h>
37 /* Part of U-boot ABI: see head.S */
49 /* ID.ARCVER, Release */
62 /* UARCH.MAJOR, Release */
70 static void read_decode_ccm_bcr(struct cpuinfo_arc *cpu) in read_decode_ccm_bcr() argument
78 cpu->iccm.sz = 4096 << iccm.sz; /* 8K to 512K */ in read_decode_ccm_bcr()
79 cpu->iccm.base_addr = iccm.base << 16; in read_decode_ccm_bcr()
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| /Linux-v5.10/arch/arm/mach-axxia/ |
| D | platsmp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-axxia/platsmp.c
31 static int axxia_boot_secondary(unsigned int cpu, struct task_struct *idle) in axxia_boot_secondary() argument
37 syscon_np = of_find_compatible_node(NULL, NULL, "lsi,axxia-syscon"); in axxia_boot_secondary()
39 return -ENOENT; in axxia_boot_secondary()
43 return -ENOMEM; in axxia_boot_secondary()
47 tmp &= ~(1 << cpu); in axxia_boot_secondary()
56 int cpu; in axxia_smp_prepare_cpus() local
62 for_each_possible_cpu(cpu) { in axxia_smp_prepare_cpus()
66 np = of_get_cpu_node(cpu, NULL); in axxia_smp_prepare_cpus()
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| /Linux-v5.10/include/soc/fsl/ |
| D | bman.h | 1 /* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
34 /* wrapper for 48-bit buffers */
38 __be16 bpid; /* hi 8-bits reserved */
39 __be16 hi; /* High 16-bits of 48-bit address */
40 __be32 lo; /* Low 32-bits of 48-bit address */
51 return be64_to_cpu(buf->data) & 0xffffffffffffLLU; in bm_buf_addr()
56 return be64_to_cpu(buf->data) & 0xffffffffffffLLU; in bm_buffer_get64()
59 static inline void bm_buffer_set64(struct bm_buffer *buf, u64 addr) in bm_buffer_set64() argument
61 buf->hi = cpu_to_be16(upper_32_bits(addr)); in bm_buffer_set64()
62 buf->lo = cpu_to_be32(lower_32_bits(addr)); in bm_buffer_set64()
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| /Linux-v5.10/drivers/gpu/drm/armada/ |
| D | armada_gem.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/dma-buf.h>
7 #include <linux/dma-mapping.h>
20 struct drm_gem_object *gobj = vmf->vma->vm_private_data; in armada_gem_vm_fault()
22 unsigned long pfn = obj->phys_addr >> PAGE_SHIFT; in armada_gem_vm_fault()
24 pfn += (vmf->address - vmf->vma->vm_start) >> PAGE_SHIFT; in armada_gem_vm_fault()
25 return vmf_insert_pfn(vmf->vma, vmf->address, pfn); in armada_gem_vm_fault()
42 struct armada_private *priv = drm_to_armada_dev(obj->dev); in armada_gem_free_object()
44 DRM_DEBUG_DRIVER("release obj %p\n", dobj); in armada_gem_free_object()
46 drm_gem_free_mmap_offset(&dobj->obj); in armada_gem_free_object()
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| /Linux-v5.10/Documentation/arm64/ |
| D | booting.rst | 13 (EL0 - EL3), with EL0 and EL1 having a secure and a non-secure
14 counterpart. EL2 is the hypervisor level and exists only in non-secure
18 simply to define all software that executes on the CPU(s) before control
33 ---------------------------
46 -------------------------
50 The device tree blob (dtb) must be placed on an 8-byte boundary and must
59 ------------------------------
71 ------------------------
75 The decompressed kernel image contains a 64-byte header as follows::
91 - As of v3.17, all fields are little endian unless stated otherwise.
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