Lines Matching +full:cpu +full:- +full:release +full:- +full:addr
2 CPU topology binding description
6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
20 For instance in a system where CPUs support SMT, "cpu" nodes represent all
22 In systems where SMT is not supported "cpu" nodes represent all cores present
25 CPU topology bindings allow one to associate cpu nodes with hierarchical groups
29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
32 The cpu nodes, as per bindings defined in [4], represent the devices that
35 A topology description containing phandles to cpu nodes that are not compliant
39 2 - cpu-map node
42 The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct
46 - cpu-map node
48 Usage: Optional - On SMP systems provide CPUs topology to the OS.
51 cpu-map node.
53 Description: The cpu-map node is just a container node where its
54 subnodes describe the CPU topology.
56 Node name must be "cpu-map".
58 The cpu-map node's parent node must be the cpus node.
60 The cpu-map node's child nodes can be:
62 - one or more cluster nodes or
63 - one or more socket nodes in a multi-socket system
67 The cpu-map node can only contain 4 types of child nodes:
69 - socket node
70 - cluster node
71 - core node
72 - thread node
76 The nodes describing the CPU topology (socket/cluster/core/thread) can
77 only be defined within the cpu-map node and every core/thread in the
82 2.1 - cpu-map child nodes naming convention
85 cpu-map child nodes must follow a naming convention where the node name
90 cpu-map child nodes which do not share a common parent node can have the same
91 name (ie same number N as other cpu-map child nodes at different device tree
95 3 - socket/cluster/core/thread node bindings
98 Bindings for socket/cluster/cpu/thread nodes are defined as follows:
100 - socket node
102 Description: must be declared within a cpu-map node, one node
118 - cluster node
120 Description: must be declared within a cpu-map node, one node
130 - one or more cluster nodes; or
131 - one or more core nodes
135 - core node
148 - cpu
151 Definition: a phandle to the cpu node that corresponds to the
157 - one or more thread nodes
161 - thread node
173 - cpu
176 Definition: a phandle to the cpu node that corresponds to
180 4 - Example dts
183 Example 1 (ARM 64-bit, 16-cpu system, two clusters of clusters in a single
187 #size-cells = <0>;
188 #address-cells = <2>;
190 cpu-map {
196 cpu = <&CPU0>;
199 cpu = <&CPU1>;
205 cpu = <&CPU2>;
208 cpu = <&CPU3>;
216 cpu = <&CPU4>;
219 cpu = <&CPU5>;
225 cpu = <&CPU6>;
228 cpu = <&CPU7>;
238 cpu = <&CPU8>;
241 cpu = <&CPU9>;
246 cpu = <&CPU10>;
249 cpu = <&CPU11>;
257 cpu = <&CPU12>;
260 cpu = <&CPU13>;
265 cpu = <&CPU14>;
268 cpu = <&CPU15>;
276 CPU0: cpu@0 {
277 device_type = "cpu";
278 compatible = "arm,cortex-a57";
280 enable-method = "spin-table";
281 cpu-release-addr = <0 0x20000000>;
284 CPU1: cpu@1 {
285 device_type = "cpu";
286 compatible = "arm,cortex-a57";
288 enable-method = "spin-table";
289 cpu-release-addr = <0 0x20000000>;
292 CPU2: cpu@100 {
293 device_type = "cpu";
294 compatible = "arm,cortex-a57";
296 enable-method = "spin-table";
297 cpu-release-addr = <0 0x20000000>;
300 CPU3: cpu@101 {
301 device_type = "cpu";
302 compatible = "arm,cortex-a57";
304 enable-method = "spin-table";
305 cpu-release-addr = <0 0x20000000>;
308 CPU4: cpu@10000 {
309 device_type = "cpu";
310 compatible = "arm,cortex-a57";
312 enable-method = "spin-table";
313 cpu-release-addr = <0 0x20000000>;
316 CPU5: cpu@10001 {
317 device_type = "cpu";
318 compatible = "arm,cortex-a57";
320 enable-method = "spin-table";
321 cpu-release-addr = <0 0x20000000>;
324 CPU6: cpu@10100 {
325 device_type = "cpu";
326 compatible = "arm,cortex-a57";
328 enable-method = "spin-table";
329 cpu-release-addr = <0 0x20000000>;
332 CPU7: cpu@10101 {
333 device_type = "cpu";
334 compatible = "arm,cortex-a57";
336 enable-method = "spin-table";
337 cpu-release-addr = <0 0x20000000>;
340 CPU8: cpu@100000000 {
341 device_type = "cpu";
342 compatible = "arm,cortex-a57";
344 enable-method = "spin-table";
345 cpu-release-addr = <0 0x20000000>;
348 CPU9: cpu@100000001 {
349 device_type = "cpu";
350 compatible = "arm,cortex-a57";
352 enable-method = "spin-table";
353 cpu-release-addr = <0 0x20000000>;
356 CPU10: cpu@100000100 {
357 device_type = "cpu";
358 compatible = "arm,cortex-a57";
360 enable-method = "spin-table";
361 cpu-release-addr = <0 0x20000000>;
364 CPU11: cpu@100000101 {
365 device_type = "cpu";
366 compatible = "arm,cortex-a57";
368 enable-method = "spin-table";
369 cpu-release-addr = <0 0x20000000>;
372 CPU12: cpu@100010000 {
373 device_type = "cpu";
374 compatible = "arm,cortex-a57";
376 enable-method = "spin-table";
377 cpu-release-addr = <0 0x20000000>;
380 CPU13: cpu@100010001 {
381 device_type = "cpu";
382 compatible = "arm,cortex-a57";
384 enable-method = "spin-table";
385 cpu-release-addr = <0 0x20000000>;
388 CPU14: cpu@100010100 {
389 device_type = "cpu";
390 compatible = "arm,cortex-a57";
392 enable-method = "spin-table";
393 cpu-release-addr = <0 0x20000000>;
396 CPU15: cpu@100010101 {
397 device_type = "cpu";
398 compatible = "arm,cortex-a57";
400 enable-method = "spin-table";
401 cpu-release-addr = <0 0x20000000>;
405 Example 2 (ARM 32-bit, dual-cluster, 8-cpu system, no SMT):
408 #size-cells = <0>;
409 #address-cells = <1>;
411 cpu-map {
414 cpu = <&CPU0>;
417 cpu = <&CPU1>;
420 cpu = <&CPU2>;
423 cpu = <&CPU3>;
429 cpu = <&CPU4>;
432 cpu = <&CPU5>;
435 cpu = <&CPU6>;
438 cpu = <&CPU7>;
443 CPU0: cpu@0 {
444 device_type = "cpu";
445 compatible = "arm,cortex-a15";
449 CPU1: cpu@1 {
450 device_type = "cpu";
451 compatible = "arm,cortex-a15";
455 CPU2: cpu@2 {
456 device_type = "cpu";
457 compatible = "arm,cortex-a15";
461 CPU3: cpu@3 {
462 device_type = "cpu";
463 compatible = "arm,cortex-a15";
467 CPU4: cpu@100 {
468 device_type = "cpu";
469 compatible = "arm,cortex-a7";
473 CPU5: cpu@101 {
474 device_type = "cpu";
475 compatible = "arm,cortex-a7";
479 CPU6: cpu@102 {
480 device_type = "cpu";
481 compatible = "arm,cortex-a7";
485 CPU7: cpu@103 {
486 device_type = "cpu";
487 compatible = "arm,cortex-a7";
492 Example 3: HiFive Unleashed (RISC-V 64 bit, 4 core system)
495 #address-cells = <2>;
496 #size-cells = <2>;
498 model = "sifive,hifive-unleashed-a00";
502 #address-cells = <1>;
503 #size-cells = <0>;
504 cpu-map {
508 cpu = <&CPU1>;
511 cpu = <&CPU2>;
523 CPU1: cpu@1 {
524 device_type = "cpu";
529 CPU2: cpu@2 {
530 device_type = "cpu";
534 CPU3: cpu@3 {
535 device_type = "cpu";
539 CPU4: cpu@4 {
540 device_type = "cpu";
551 [3] RISC-V Linux kernel documentation