Lines Matching +full:cpu +full:- +full:release +full:- +full:addr
1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "stih418-clock.dtsi"
7 #include "stih407-family.dtsi"
8 #include "stih410-pinctrl.dtsi"
11 #address-cells = <1>;
12 #size-cells = <0>;
13 cpu@2 {
14 device_type = "cpu";
15 compatible = "arm,cortex-a9";
17 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
18 cpu-release-addr = <0x94100A4>;
20 cpu@3 {
21 device_type = "cpu";
22 compatible = "arm,cortex-a9";
24 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
25 cpu-release-addr = <0x94100A4>;
31 compatible = "st,stih407-usb2-phy";
33 #phy-cells = <0>;
37 reset-names = "global", "port";
41 compatible = "st,stih407-usb2-phy";
43 #phy-cells = <0>;
47 reset-names = "global", "port";
51 compatible = "st,st-ohci-300x";
57 reset-names = "power", "softreset";
59 phy-names = "usb";
63 compatible = "st,st-ehci-300x";
66 pinctrl-names = "default";
67 pinctrl-0 = <&pinctrl_usb0>;
71 reset-names = "power", "softreset";
73 phy-names = "usb";
77 compatible = "st,st-ohci-300x";
83 reset-names = "power", "softreset";
85 phy-names = "usb";
89 compatible = "st,st-ehci-300x";
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_usb1>;
97 reset-names = "power", "softreset";
99 phy-names = "usb";
103 assigned-clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
104 assigned-clock-parents = <&clk_s_c0_pll1 0>;
105 assigned-clock-rates = <200000000>;