Lines Matching +full:cpu +full:- +full:release +full:- +full:addr
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
4 * Copyright 2016-2018 NXP
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
23 #address-cells = <2>;
24 #size-cells = <0>;
26 cpu0: cpu@0 {
27 device_type = "cpu";
28 compatible = "arm,cortex-a53";
30 enable-method = "spin-table";
31 cpu-release-addr = <0x0 0x80000000>;
32 next-level-cache = <&cluster0_l2_cache>;
35 cpu1: cpu@1 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a53";
39 enable-method = "spin-table";
40 cpu-release-addr = <0x0 0x80000000>;
41 next-level-cache = <&cluster0_l2_cache>;
44 cpu2: cpu@100 {
45 device_type = "cpu";
46 compatible = "arm,cortex-a53";
48 enable-method = "spin-table";
49 cpu-release-addr = <0x0 0x80000000>;
50 next-level-cache = <&cluster1_l2_cache>;
53 cpu3: cpu@101 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a53";
57 enable-method = "spin-table";
58 cpu-release-addr = <0x0 0x80000000>;
59 next-level-cache = <&cluster1_l2_cache>;
62 cluster0_l2_cache: l2-cache0 {
66 cluster1_l2_cache: l2-cache1 {
72 compatible = "arm,armv8-timer";
81 /* clock-frequency might be modified by u-boot, depending on the
84 clock-frequency = <10000000>;
87 gic: interrupt-controller@7d001000 {
88 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
89 #interrupt-cells = <3>;
90 #address-cells = <0>;
91 interrupt-controller;
101 #address-cells = <2>;
102 #size-cells = <2>;
103 compatible = "simple-bus";
104 interrupt-parent = <&gic>;
108 compatible = "simple-bus";
109 #address-cells = <2>;
110 #size-cells = <2>;
111 interrupt-parent = <&gic>;
116 compatible = "fsl,s32v234-linflexuart";
124 compatible = "simple-bus";
125 #address-cells = <2>;
126 #size-cells = <2>;
127 interrupt-parent = <&gic>;
132 compatible = "fsl,s32v234-linflexuart";