Lines Matching +full:cpu +full:- +full:release +full:- +full:addr
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * (C) Copyright 2018 - 2020, Toshiba Corporation.
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 /memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */
17 #address-cells = <2>;
18 #size-cells = <2>;
21 #address-cells = <1>;
22 #size-cells = <0>;
24 cpu-map {
27 cpu = <&cpu0>;
30 cpu = <&cpu1>;
33 cpu = <&cpu2>;
36 cpu = <&cpu3>;
42 cpu = <&cpu4>;
45 cpu = <&cpu5>;
48 cpu = <&cpu6>;
51 cpu = <&cpu7>;
56 cpu0: cpu@0 {
57 compatible = "arm,cortex-a53";
58 device_type = "cpu";
59 enable-method = "spin-table";
60 cpu-release-addr = <0x0 0x81100000>;
64 cpu1: cpu@1 {
65 compatible = "arm,cortex-a53";
66 device_type = "cpu";
67 enable-method = "spin-table";
68 cpu-release-addr = <0x0 0x81100000>;
72 cpu2: cpu@2 {
73 compatible = "arm,cortex-a53";
74 device_type = "cpu";
75 enable-method = "spin-table";
76 cpu-release-addr = <0x0 0x81100000>;
80 cpu3: cpu@3 {
81 compatible = "arm,cortex-a53";
82 device_type = "cpu";
83 enable-method = "spin-table";
84 cpu-release-addr = <0x0 0x81100000>;
88 cpu4: cpu@100 {
89 compatible = "arm,cortex-a53";
90 device_type = "cpu";
91 enable-method = "spin-table";
92 cpu-release-addr = <0x0 0x81100000>;
96 cpu5: cpu@101 {
97 compatible = "arm,cortex-a53";
98 device_type = "cpu";
99 enable-method = "spin-table";
100 cpu-release-addr = <0x0 0x81100000>;
104 cpu6: cpu@102 {
105 compatible = "arm,cortex-a53";
106 device_type = "cpu";
107 enable-method = "spin-table";
108 cpu-release-addr = <0x0 0x81100000>;
112 cpu7: cpu@103 {
113 compatible = "arm,cortex-a53";
114 device_type = "cpu";
115 enable-method = "spin-table";
116 cpu-release-addr = <0x0 0x81100000>;
122 compatible = "arm,armv8-timer";
123 interrupt-parent = <&gic>;
131 uart_clk: uart-clk {
132 compatible = "fixed-clock";
133 clock-frequency = <150000000>;
134 #clock-cells = <0>;
138 #address-cells = <2>;
139 #size-cells = <2>;
140 compatible = "simple-bus";
141 interrupt-parent = <&gic>;
144 gic: interrupt-controller@24001000 {
145 compatible = "arm,gic-400";
146 interrupt-controller;
147 #interrupt-cells = <3>;
156 compatible = "toshiba,tmpv7708-pinctrl";
164 pinctrl-names = "default";
165 pinctrl-0 = <&uart0_pins>;
173 pinctrl-names = "default";
174 pinctrl-0 = <&uart1_pins>;
182 pinctrl-names = "default";
183 pinctrl-0 = <&uart2_pins>;
191 pinctrl-names = "default";
192 pinctrl-0 = <&uart3_pins>;
197 compatible = "snps,designware-i2c";
200 pinctrl-names = "default";
201 pinctrl-0 = <&i2c0_pins>;
202 clock-frequency = <400000>;
203 #address-cells = <1>;
204 #size-cells = <0>;
209 compatible = "snps,designware-i2c";
212 pinctrl-names = "default";
213 pinctrl-0 = <&i2c1_pins>;
214 clock-frequency = <400000>;
215 #address-cells = <1>;
216 #size-cells = <0>;
221 compatible = "snps,designware-i2c";
224 pinctrl-names = "default";
225 pinctrl-0 = <&i2c2_pins>;
226 clock-frequency = <400000>;
227 #address-cells = <1>;
228 #size-cells = <0>;
233 compatible = "snps,designware-i2c";
236 pinctrl-names = "default";
237 pinctrl-0 = <&i2c3_pins>;
238 clock-frequency = <400000>;
239 #address-cells = <1>;
240 #size-cells = <0>;
245 compatible = "snps,designware-i2c";
248 pinctrl-names = "default";
249 pinctrl-0 = <&i2c4_pins>;
250 clock-frequency = <400000>;
251 #address-cells = <1>;
252 #size-cells = <0>;
257 compatible = "snps,designware-i2c";
260 pinctrl-names = "default";
261 pinctrl-0 = <&i2c5_pins>;
262 clock-frequency = <400000>;
263 #address-cells = <1>;
264 #size-cells = <0>;
269 compatible = "snps,designware-i2c";
272 pinctrl-names = "default";
273 pinctrl-0 = <&i2c6_pins>;
274 clock-frequency = <400000>;
275 #address-cells = <1>;
276 #size-cells = <0>;
281 compatible = "snps,designware-i2c";
284 pinctrl-names = "default";
285 pinctrl-0 = <&i2c7_pins>;
286 clock-frequency = <400000>;
287 #address-cells = <1>;
288 #size-cells = <0>;
293 compatible = "snps,designware-i2c";
296 pinctrl-names = "default";
297 pinctrl-0 = <&i2c8_pins>;
298 clock-frequency = <400000>;
299 #address-cells = <1>;
300 #size-cells = <0>;
308 pinctrl-names = "default";
309 pinctrl-0 = <&spi0_pins>;
310 num-cs = <1>;
311 #address-cells = <1>;
312 #size-cells = <0>;
320 pinctrl-names = "default";
321 pinctrl-0 = <&spi1_pins>;
322 num-cs = <1>;
323 #address-cells = <1>;
324 #size-cells = <0>;
332 pinctrl-names = "default";
333 pinctrl-0 = <&spi2_pins>;
334 num-cs = <1>;
335 #address-cells = <1>;
336 #size-cells = <0>;
344 pinctrl-names = "default";
345 pinctrl-0 = <&spi3_pins>;
346 num-cs = <1>;
347 #address-cells = <1>;
348 #size-cells = <0>;
356 pinctrl-names = "default";
357 pinctrl-0 = <&spi4_pins>;
358 num-cs = <1>;
359 #address-cells = <1>;
360 #size-cells = <0>;
368 pinctrl-names = "default";
369 pinctrl-0 = <&spi5_pins>;
370 num-cs = <1>;
371 #address-cells = <1>;
372 #size-cells = <0>;
380 pinctrl-names = "default";
381 pinctrl-0 = <&spi6_pins>;
382 num-cs = <1>;
383 #address-cells = <1>;
384 #size-cells = <0>;