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/Linux-v5.10/Documentation/admin-guide/pm/
Dintel-speed-select.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Intel(R) Speed Select Technology User Guide
7 The Intel(R) Speed Select Technology (Intel(R) SST) provides a powerful new
14 - https://www.intel.com/content/www/us/en/architecture-and-technology/speed-select-technology-artic…
15 - https://builders.intel.com/docs/networkbuilders/intel-speed-select-technology-base-frequency-enha…
19 dynamically without pre-configuring via BIOS setup options. This dynamic
21 and configure these features is by using the Intel Speed Select utility.
23 This document explains how to use the Intel Speed Select tool to enumerate and
29 intel-speed-select configuration tool
32 Most Linux distribution packages may include the "intel-speed-select" tool. If not,
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/Linux-v5.10/Documentation/ABI/testing/
Dsysfs-bus-pci-drivers-ehci_hcd7 PCI-based EHCI USB controllers (i.e., high-speed USB-2.0
9 "companion" full/low-speed USB-1.1 controllers. When a
10 high-speed device is plugged in, the connection is routed
11 to the EHCI controller; when a full- or low-speed device
15 Sometimes you want to force a high-speed device to connect
16 at full speed, which can be accomplished by forcing the
23 For example: To force the high-speed device attached to
24 port 4 on bus 2 to run at full speed::
28 To return the port to high-speed operation::
30 echo -4 >/sys/bus/usb/devices/usb2/../companion
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/Linux-v5.10/Documentation/hwmon/
Dadm9240.rst10 Addresses scanned: I2C 0x2c - 0x2f
20 Addresses scanned: I2C 0x2c - 0x2f
24 http://pdfserv.maxim-ic.com/en/ds/DS1780.pdf
30 Addresses scanned: I2C 0x2c - 0x2f
37 - Frodo Looijaard <frodol@dds.nl>,
38 - Philip Edelbrock <phil@netroedge.com>,
39 - Michiel Rook <michiel@grendelproject.nl>,
40 - Grant Coady <gcoady.lk@gmail.com> with guidance
44 ---------
46 chip MSB 5-bit address. Each chip reports a unique manufacturer
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Dvt1211.rst10 Addresses scanned: none, address read from Super-I/O config space
24 -----------------
29 configuration for channels 1-5.
30 Legal values are in the range of 0-31. Bit 0 maps to
47 -----------
49 The VIA VT1211 Super-I/O chip includes complete hardware monitoring
52 implements 5 universal input channels (UCH1-5) that can be individually
60 connected to the PWM outputs of the VT1211 :-().
80 ------------------
82 Voltages are sampled by an 8-bit ADC with a LSB of ~10mV. The supported input
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Dw83792d.rst10 Addresses scanned: I2C 0x2c - 0x2f
19 -----------------
35 -----------
42 parameter; this will put it into a more well-behaved state first.
44 The driver implements three temperature sensors, seven fan rotation speed
48 The driver also implements up to seven fan control outputs: pwm1-7. Pwm1-7
53 Automatic fan control mode is possible only for fan1-fan3.
55 For all pwmX outputs, a value of 0 means minimum fan speed and a value of
56 255 means maximum fan speed.
64 triggered if the rotation speed has dropped below a programmable limit. Fan
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/Linux-v5.10/drivers/usb/gadget/udc/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
7 # NOTE: Gadget support ** DOES NOT ** depend on host-side CONFIG_USB !!
9 # - Host systems (like PCs) need CONFIG_USB (with "A" jacks).
10 # - Peripherals (like PDAs) need CONFIG_USB_GADGET (with "B" jacks).
11 # - Some systems have both kinds of controllers.
13 # With help from a special transceiver and a "Mini-AB" jack, systems with
14 # both kinds of controller can also support "USB On-the-Go" (CONFIG_USB_OTG).
22 # - integrated/SOC controllers first
23 # - licensed IP used in both SOC and discrete versions
24 # - discrete ones (including all PCI-only controllers)
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/Linux-v5.10/Documentation/usb/
Dehci.rst5 27-Dec-2002
7 The EHCI driver is used to talk to high speed USB 2.0 devices using
8 USB 2.0-capable host controller hardware. The USB 2.0 standard is
11 - "High Speed" 480 Mbit/sec (60 MByte/sec)
12 - "Full Speed" 12 Mbit/sec (1.5 MByte/sec)
13 - "Low Speed" 1.5 Mbit/sec
15 USB 1.1 only addressed full speed and low speed. High speed devices
23 (TT) in the hub, which turns low or full speed transactions into
24 high speed "split transactions" that don't waste transfer bandwidth.
31 While usb-storage devices have been available since mid-2001 (working
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/Linux-v5.10/drivers/usb/gadget/function/
Du_uvc.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 * Copyright (c) 2013-2014 Samsung Electronics Co., Ltd.
32 * Control descriptors array pointers for full-/high-speed and
33 * super-speed. They point by default to the uvc_fs_control_cls and
41 * Streaming descriptors array pointers for full-speed, high-speed and
42 * super-speed. They will point to the uvc_[fhs]s_streaming_cls arrays
43 * for configfs-based gadgets. Legacy gadgets must initialize them in
50 /* Default control descriptors for configfs-based gadgets. */
57 * Control descriptors pointers arrays for full-/high-speed and
58 * super-speed. The first element is a configurable control header
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/Linux-v5.10/drivers/phy/qualcomm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
26 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
58 controllers on Qualcomm chips. This driver supports the high-speed
65 depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
68 Support for the USB high-speed ULPI compliant phy on Qualcomm
76 Enable support for the USB high-speed SNPS Femto phy on Qualcomm
89 tristate "Qualcomm 28nm High-Speed PHY"
91 depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
95 High-Speed PHY driver. This driver supports the Hi-Speed PHY which
100 tristate "Qualcomm USB Super-Speed PHY driver"
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/Linux-v5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu7_thermal.c32 if (hwmgr->thermal_controller.fanInfo.bNoFan) in smu7_fan_ctrl_get_fan_speed_info()
33 return -ENODEV; in smu7_fan_ctrl_get_fan_speed_info()
35 fan_speed_info->supports_percent_read = true; in smu7_fan_ctrl_get_fan_speed_info()
36 fan_speed_info->supports_percent_write = true; in smu7_fan_ctrl_get_fan_speed_info()
37 fan_speed_info->min_percent = 0; in smu7_fan_ctrl_get_fan_speed_info()
38 fan_speed_info->max_percent = 100; in smu7_fan_ctrl_get_fan_speed_info()
41 hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) { in smu7_fan_ctrl_get_fan_speed_info()
42 fan_speed_info->supports_rpm_read = true; in smu7_fan_ctrl_get_fan_speed_info()
43 fan_speed_info->supports_rpm_write = true; in smu7_fan_ctrl_get_fan_speed_info()
44 fan_speed_info->min_rpm = hwmgr->thermal_controller.fanInfo.ulMinRPM; in smu7_fan_ctrl_get_fan_speed_info()
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Dvega20_thermal.c34 struct vega20_hwmgr *data = hwmgr->backend; in vega20_disable_fan_control_feature()
37 if (data->smu_features[GNLD_FAN_CONTROL].supported) { in vega20_disable_fan_control_feature()
40 data->smu_features[GNLD_FAN_CONTROL]. in vega20_disable_fan_control_feature()
45 data->smu_features[GNLD_FAN_CONTROL].enabled = false; in vega20_disable_fan_control_feature()
53 struct vega20_hwmgr *data = hwmgr->backend; in vega20_fan_ctrl_stop_smc_fan_control()
55 if (data->smu_features[GNLD_FAN_CONTROL].supported) in vega20_fan_ctrl_stop_smc_fan_control()
63 struct vega20_hwmgr *data = hwmgr->backend; in vega20_enable_fan_control_feature()
66 if (data->smu_features[GNLD_FAN_CONTROL].supported) { in vega20_enable_fan_control_feature()
69 data->smu_features[GNLD_FAN_CONTROL]. in vega20_enable_fan_control_feature()
74 data->smu_features[GNLD_FAN_CONTROL].enabled = true; in vega20_enable_fan_control_feature()
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Dvega10_thermal.c42 if (hwmgr->thermal_controller.fanInfo.bNoFan) in vega10_fan_ctrl_get_fan_speed_info()
45 fan_speed_info->supports_percent_read = true; in vega10_fan_ctrl_get_fan_speed_info()
46 fan_speed_info->supports_percent_write = true; in vega10_fan_ctrl_get_fan_speed_info()
47 fan_speed_info->min_percent = 0; in vega10_fan_ctrl_get_fan_speed_info()
48 fan_speed_info->max_percent = 100; in vega10_fan_ctrl_get_fan_speed_info()
51 hwmgr->thermal_controller.fanInfo. in vega10_fan_ctrl_get_fan_speed_info()
53 fan_speed_info->supports_rpm_read = true; in vega10_fan_ctrl_get_fan_speed_info()
54 fan_speed_info->supports_rpm_write = true; in vega10_fan_ctrl_get_fan_speed_info()
55 fan_speed_info->min_rpm = in vega10_fan_ctrl_get_fan_speed_info()
56 hwmgr->thermal_controller.fanInfo.ulMinRPM; in vega10_fan_ctrl_get_fan_speed_info()
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/Linux-v5.10/include/linux/platform_data/
Ds3c-hsudc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * S3C24XX USB 2.0 High-speed USB controller gadget driver
8 * The S3C24XX USB 2.0 high-speed USB controller supports upto 9 endpoints.
17 * s3c24xx_hsudc_platdata - Platform data for USB High-Speed gadget controller.
22 * Representation of platform data for the S3C24XX USB 2.0 High Speed gadget
/Linux-v5.10/Documentation/devicetree/bindings/powerpc/4xx/
Dhsta.txt2 ppc476gtr High Speed Serial Assist (HSTA) node
5 The 476gtr SoC contains a high speed serial assist module attached
6 between the plb4 and plb6 system buses to provide high speed data
14 - compatible : "ibm,476gtr-hsta-msi", "ibm,hsta-msi"
15 - reg : register mapping for the HSTA MSI space
16 - interrupts : ordered interrupt mapping for each MSI in the register
/Linux-v5.10/Documentation/devicetree/bindings/i2c/
Di2c-exynos5.txt1 * Samsung's High Speed I2C controller
3 The Samsung's High Speed I2C controller is used to interface with I2C devices
7 - compatible: value should be.
8 -> "samsung,exynos5-hsi2c", (DEPRECATED)
11 -> "samsung,exynos5250-hsi2c", for i2c compatible with HSI2C available
13 -> "samsung,exynos5260-hsi2c", for i2c compatible with HSI2C available
15 -> "samsung,exynos7-hsi2c", for i2c compatible with HSI2C available
18 - reg: physical base address of the controller and length of memory mapped
20 - interrupts: interrupt number to the cpu.
21 - #address-cells: always 1 (for i2c addresses)
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/Linux-v5.10/arch/arm/boot/dts/
Dstih410-b2260.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
12 compatible = "st,stih410-b2260", "st,stih410";
16 stdout-path = &uart1;
30 compatible = "gpio-leds";
34 linux,default-trigger = "heartbeat";
35 default-state = "off";
41 default-state = "off";
47 default-state = "off";
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Dsocfpga_cyclone5_chameleon96.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
14 compatible = "novtech,chameleon96", "altr,socfpga-cyclone5", "altr,socfpga";
18 stdout-path = "serial0:115200n8";
27 regulator_3_3v: 3-3-v-regulator {
28 compatible = "regulator-fixed";
29 regulator-name = "3.3V";
30 regulator-min-microvolt = <3300000>;
31 regulator-max-microvolt = <3300000>;
35 compatible = "gpio-leds";
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/Linux-v5.10/Documentation/devicetree/bindings/mmc/
Dmmc-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
25 "#address-cells":
30 "#size-cells":
37 broken-cd:
42 cd-gpios:
46 non-removable:
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Dcdns,sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
11 - Piotr Sroka <piotrs@cadence.com>
14 - $ref: mmc-controller.yaml
19 - enum:
20 - socionext,uniphier-sd4hc
21 - const: cdns,sd4hc
37 cdns,phy-input-delay-sd-highspeed:
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/Linux-v5.10/drivers/gpu/drm/amd/display/dc/dce/
Ddce_i2c_sw.c38 dce_i2c_sw->ctx = ctx; in dce_i2c_sw_construct()
48 dal_gpio_get_value(ddc->pin_data, &value); in read_bit_from_ddc()
50 dal_gpio_get_value(ddc->pin_clock, &value); in read_bit_from_ddc()
63 dal_gpio_set_value(ddc->pin_data, value); in write_bit_to_ddc()
65 dal_gpio_set_value(ddc->pin_clock, value); in write_bit_to_ddc()
72 dal_ddc_close(dce_i2c_sw->ddc); in release_engine_dce_sw()
73 dce_i2c_sw->ddc = NULL; in release_engine_dce_sw()
122 --shift; in write_byte_sw()
125 /* The display sends ACK by preventing the SDA from going high in write_byte_sw()
127 * If the SDA goes high after that bit, it's a NACK in write_byte_sw()
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/Linux-v5.10/Documentation/devicetree/bindings/phy/
Dsocionext,uniphier-usb3hs-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 High-Speed (HS) PHY
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about High-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-usb3-hsphy
22 - socionext,uniphier-pxs2-usb3-hsphy
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/Linux-v5.10/drivers/usb/dwc2/
Dhcd.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * hcd.h - DesignWare HS OTG Controller host-mode declarations
5 * Copyright (C) 2004-2013 Synopsys, Inc.
16 * 3. The names of the above-listed copyright holders may not be used
53 * struct dwc2_host_chan - Software host channel descriptor
59 * @speed: Device speed. One of the following values:
60 * - USB_SPEED_LOW
61 * - USB_SPEED_FULL
62 * - USB_SPEED_HIGH
64 * - USB_ENDPOINT_XFER_CONTROL: 0
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/Linux-v5.10/drivers/infiniband/hw/hfi1/
Dmad.h2 * Copyright(c) 2015 - 2017 Intel Corporation.
24 * - Redistributions of source code must retain the above copyright
26 * - Redistributions in binary form must reproduce the above copyright
30 * - Neither the name of Intel Corporation nor the names of its
82 #define OPA_NOTICE_TRAP_LSE_CHG 0x04 /* Link Speed Enable changed */
142 u8 sl; /* SL: high 5 bits */
146 __be32 qp1; /* high 8 bits reserved */
147 __be32 qp2; /* high 8 bits reserved */
155 u8 sl; /* SL: high 5 bits */
159 __be32 qp1; /* high 8 bits reserved */
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/Linux-v5.10/Documentation/devicetree/bindings/
Dxilinx.txt10 Each IP-core has a set of parameters which the FPGA designer can use to
20 properties of the device node. In general, device nodes for IP-cores
23 (name): (generic-name)@(base-address) {
24 compatible = "xlnx,(ip-core-name)-(HW_VER)"
27 interrupt-parent = <&interrupt-controller-phandle>;
29 xlnx,(parameter1) = "(string-value)";
30 xlnx,(parameter2) = <(int-value)>;
33 (generic-name): an open firmware-style name that describes the
36 (ip-core-name): the name of the ip block (given after the BEGIN
38 and all underscores '_' converted to dashes '-'.
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/Linux-v5.10/Documentation/devicetree/bindings/usb/
Dsamsung-hsotg.txt1 Samsung High Speed USB OTG controller
2 -----------------------------
5 It gives functionality of OTG-compliant USB 2.0 host and device with
6 support for USB 2.0 high-speed (480Mbps) and full-speed (12 Mbps)
12 -----
15 - compatible: "samsung,s3c6400-hsotg" should be used for all currently
17 - interrupts: specifier of interrupt signal of interrupt controller,
19 - clocks: contains an array of clock specifiers:
20 - first entry: OTG clock
21 - clock-names: contains array of clock names:
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