Lines Matching +full:high +full:- +full:speed

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 High-Speed (HS) PHY
12   Although the controller includes High-Speed PHY and Super-Speed PHY,
13   this describes about High-Speed PHY.
16   - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21       - socionext,uniphier-pro5-usb3-hsphy
22       - socionext,uniphier-pxs2-usb3-hsphy
23       - socionext,uniphier-ld20-usb3-hsphy
24       - socionext,uniphier-pxs3-usb3-hsphy
29   "#phy-cells":
36   clock-names:
38       - const: link          # for PXs2
39       - items:               # for PXs3 with phy-ext
40           - const: link
41           - const: phy
42           - const: phy-ext
43       - items:               # for others
44           - const: link
45           - const: phy
50   reset-names:
52       - const: link
53       - const: phy
55   vbus-supply:
58   nvmem-cells:
62       Available only for HS-PHY implemented on LD20 and PXs3, and
65   nvmem-cell-names:
67       - const: rterm
68       - const: sel_t
69       - const: hs_i
71       Should be the following names, which correspond to each nvmem-cells.
77   - compatible
78   - reg
79   - "#phy-cells"
80   - clocks
81   - clock-names
82   - resets
83   - reset-names
88   - |
89     usb-glue@65b00000 {
90         compatible = "socionext,uniphier-ld20-dwc3-glue", "simple-mfd";
91         #address-cells = <1>;
92         #size-cells = <1>;
95         usb_hsphy0: hs-phy@200 {
96             compatible = "socionext,uniphier-ld20-usb3-hsphy";
98             #phy-cells = <0>;
99             clock-names = "link", "phy";
101             reset-names = "link", "phy";
103             vbus-supply = <&usb_vbus0>;
104             nvmem-cell-names = "rterm", "sel_t", "hs_i";
105             nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, <&usb_hs_i0>;