Lines Matching +full:high +full:- +full:speed
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
25 "#address-cells":
30 "#size-cells":
37 broken-cd:
42 cd-gpios:
46 non-removable:
49 Non-removable slot (like eMMC); assume always present.
55 # low." Therefore, using the "cd-inverted" property means, that the
56 # CD line is active high, i.e. it is high, when a card is
57 # inserted. Similar logic applies to the "wp-inverted" property.
60 # ways: as GPIOs, specified in cd-gpios and wp-gpios properties, or
62 # using *-inverted properties. GPIO polarity can also be specified
67 # respective *-inverted property property results in a
68 # double-inversion and actually means the "normal" line polarity is
70 wp-inverted:
75 cd-inverted:
82 bus-width:
89 max-frequency:
96 disable-wp:
99 When set, no physical write-protect line is present. This
101 dedicated write-protect detection logic. If a GPIO is always used
102 for the write-protect detection logic, it is sufficient to not
103 specify the wp-gpios property in the absence of a write-protect
106 wp-gpios:
108 GPIO to use for the write-protect detection.
110 cd-debounce-delay-ms:
115 no-1-8-v:
121 cap-sd-highspeed:
124 SD high-speed timing is supported.
126 cap-mmc-highspeed:
129 MMC high-speed timing is supported.
131 sd-uhs-sdr12:
134 SD UHS SDR12 speed is supported.
136 sd-uhs-sdr25:
139 SD UHS SDR25 speed is supported.
141 sd-uhs-sdr50:
144 SD UHS SDR50 speed is supported.
146 sd-uhs-sdr104:
149 SD UHS SDR104 speed is supported.
151 sd-uhs-ddr50:
154 SD UHS DDR50 speed is supported.
156 cap-power-off-card:
161 cap-mmc-hw-reset:
166 cap-sdio-irq:
171 full-pwr-cycle:
176 full-pwr-cycle-in-suspend:
181 mmc-ddr-1_2v:
184 eMMC high-speed DDR mode (1.2V I/O) is supported.
186 mmc-ddr-1_8v:
189 eMMC high-speed DDR mode (1.8V I/O) is supported.
191 mmc-ddr-3_3v:
194 eMMC high-speed DDR mode (3.3V I/O) is supported.
196 mmc-hs200-1_2v:
201 mmc-hs200-1_8v:
206 mmc-hs400-1_2v:
211 mmc-hs400-1_8v:
216 mmc-hs400-enhanced-strobe:
229 no-sdio:
235 no-sd:
240 no-mmc:
246 fixed-emmc-driver-type:
248 For non-removable eMMC, enforce this driver type. The value is
255 post-power-on-delay-ms:
257 It was invented for MMC pwrseq-simple which could be referred to
258 mmc-pwrseq-simple.txt. But now it\'s reused as a tunable delay
260 regardless of whether pwrseq-simple is used. Default to 10ms if
265 supports-cqe:
271 disable-cqe-dcmd:
278 keep-power-in-suspend:
283 # Deprecated: enable-sdio-wakeup
284 wakeup-source:
289 vmmc-supply:
293 vqmmc-supply:
297 mmc-pwrseq:
300 System-on-Chip designs may specify a specific MMC power
305 "^.*@[0-9]+$":
323 - minimum: 0
330 broken-hpi:
333 Use this to indicate that the mmc-card has a broken hpi
337 - reg
339 "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
340 $ref: /schemas/types.yaml#/definitions/uint32-array
349 controller while switching to particular speed mode. These values
353 cd-debounce-delay-ms: [ cd-gpios ]
354 fixed-emmc-driver-type: [ non-removable ]
359 - |
364 bus-width = <4>;
365 cd-gpios = <&gpio 69 0>;
366 cd-inverted;
367 wp-gpios = <&gpio 70 0>;
368 max-frequency = <50000000>;
369 keep-power-in-suspend;
370 wakeup-source;
371 mmc-pwrseq = <&sdhci0_pwrseq>;
372 clk-phase-sd-hs = <63>, <72>;
375 - |
377 #address-cells = <1>;
378 #size-cells = <0>;
380 pinctrl-names = "default";
381 pinctrl-0 = <&mmc3_pins_a>;
382 vmmc-supply = <®_vmmc3>;
383 bus-width = <4>;
384 non-removable;
385 mmc-pwrseq = <&sdhci0_pwrseq>;
389 compatible = "brcm,bcm43xx-fmac";
390 interrupt-parent = <&pio>;
392 interrupt-names = "host-wake";