Lines Matching +full:high +full:- +full:speed
1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * hcd.h - DesignWare HS OTG Controller host-mode declarations
5 * Copyright (C) 2004-2013 Synopsys, Inc.
16 * 3. The names of the above-listed copyright holders may not be used
53 * struct dwc2_host_chan - Software host channel descriptor
59 * @speed: Device speed. One of the following values:
60 * - USB_SPEED_LOW
61 * - USB_SPEED_FULL
62 * - USB_SPEED_HIGH
64 * - USB_ENDPOINT_XFER_CONTROL: 0
65 * - USB_ENDPOINT_XFER_ISOC: 1
66 * - USB_ENDPOINT_XFER_BULK: 2
67 * - USB_ENDPOINT_XFER_INTR: 3
73 * 3: MDATA (non-Control EP),
86 * @error_state: True if the error count for this transaction is non-zero
95 * @hub_addr: Address of high speed hub for the split
96 * @hub_port: Port of the low/full speed device for the split
98 * - DWC2_HCSPLT_XACTPOS_MID
99 * - DWC2_HCSPLT_XACTPOS_BEGIN
100 * - DWC2_HCSPLT_XACTPOS_END
101 * - DWC2_HCSPLT_XACTPOS_ALL
104 * @schinfo: Scheduling micro-frame bitmap
124 unsigned speed:4; member
225 * struct dwc2_tt - dwc2 data associated with a usb_tt
242 * struct dwc2_hs_transfer_time - Info about a transfer on the high speed bus.
258 * struct dwc2_qh - Software queue head structure
262 * - USB_ENDPOINT_XFER_CONTROL
263 * - USB_ENDPOINT_XFER_BULK
264 * - USB_ENDPOINT_XFER_INT
265 * - USB_ENDPOINT_XFER_ISOC
269 * @dev_speed: Device speed. One of the following values:
270 * - USB_SPEED_LOW
271 * - USB_SPEED_FULL
272 * - USB_SPEED_HIGH
274 * non-controltransfers. Ignored for control transfers.
276 * - DWC2_HC_PID_DATA0
277 * - DWC2_HC_PID_DATA1
279 * @do_split: Full/low speed endpoint on high-speed hub requires split
285 * the host is high speed and the device is low speed this
291 * host is in high speed mode this will be a uframe. If
292 * the host is in low speed mode this will be a full frame.
298 * Always >= 1 unless the host is in low/full speed mode.
299 * @hs_transfers: Transfers that are scheduled as seen by the high speed
300 * bus. Not used if host is in low or full speed mode (but
301 * note that it IS USED if the device is low or full speed
302 * as long as the HOST is in high speed mode).
303 * @ls_start_schedule_slice: Start time (in slices) on the low speed bus
306 * "struct dwc2_tt". Not used if this device is high
307 * speed. Note that this is in "schedule slice" which
311 * is not dword-aligned
315 * @qh_list_entry: Entry for QH in either the periodic or non-periodic
324 * @wait_timer: Timer used to wait before re-queuing.
329 * @schedule_low_speed: True if we have a low/full speed component (either the
330 * host is in low/full speed mode or do_split).
331 * @want_wait: We should wait before re-queuing; only matters for non-
338 * be entered in either the non-periodic or periodic schedule.
383 * struct dwc2_qtd - Software queue transfer descriptor (QTD)
391 * - DWC2_HC_PID_DATA0
392 * - DWC2_HC_PID_DATA1
395 * @isoc_split_pos: Position of the ISOC split in full/low speed
425 * non-periodic or periodic schedule for execution. When a QTD is chosen for
463 return (struct usb_hcd *)hsotg->priv; in dwc2_hsotg_to_hcd()
470 * channel is re-assigned. In fact, subsequent handling may cause crashes
501 return pipe->ep_num; in dwc2_hcd_get_ep_num()
506 return pipe->pipe_type; in dwc2_hcd_get_pipe_type()
511 return pipe->maxp; in dwc2_hcd_get_maxp()
516 return pipe->maxp_mult; in dwc2_hcd_get_maxp_mult()
521 return pipe->dev_addr; in dwc2_hcd_get_dev_addr()
526 return pipe->pipe_type == USB_ENDPOINT_XFER_ISOC; in dwc2_hcd_is_pipe_isoc()
531 return pipe->pipe_type == USB_ENDPOINT_XFER_INT; in dwc2_hcd_is_pipe_int()
536 return pipe->pipe_type == USB_ENDPOINT_XFER_BULK; in dwc2_hcd_is_pipe_bulk()
541 return pipe->pipe_type == USB_ENDPOINT_XFER_CONTROL; in dwc2_hcd_is_pipe_control()
546 return pipe->pipe_dir == USB_DIR_IN; in dwc2_hcd_is_pipe_in()
583 list_del(&qtd->qtd_list_entry); in dwc2_hcd_qtd_unlink_and_free()
598 /* Check if QH is non-periodic */
600 ((_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_BULK || \
601 (_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_CONTROL)
611 return hc->ep_type == USB_ENDPOINT_XFER_BULK || in dbg_hc()
612 hc->ep_type == USB_ENDPOINT_XFER_CONTROL; in dbg_hc()
617 return qh->ep_type == USB_ENDPOINT_XFER_BULK || in dbg_qh()
618 qh->ep_type == USB_ENDPOINT_XFER_CONTROL; in dbg_qh()
623 return usb_pipetype(urb->pipe) == PIPE_BULK || in dbg_urb()
624 usb_pipetype(urb->pipe) == PIPE_CONTROL; in dbg_urb()
637 u16 diff = fr_idx1 - fr_idx2; in dwc2_frame_idx_num_gt()
650 return ((frame2 - frame1) & HFNUM_MAX_FRNUM) <= (HFNUM_MAX_FRNUM >> 1); in dwc2_frame_num_le()
661 ((frame1 - frame2) & HFNUM_MAX_FRNUM) < (HFNUM_MAX_FRNUM >> 1); in dwc2_frame_num_gt()
675 return (frame + HFNUM_MAX_FRNUM + 1 - dec) & HFNUM_MAX_FRNUM; in dwc2_frame_num_dec()
700 return dwc2_urb->status; in dwc2_hcd_urb_get_status()
706 return dwc2_urb->actual_length; in dwc2_hcd_urb_get_actual_length()
711 return dwc2_urb->error_count; in dwc2_hcd_urb_get_error_count()
718 dwc2_urb->iso_descs[desc_num].offset = offset; in dwc2_hcd_urb_set_iso_desc_params()
719 dwc2_urb->iso_descs[desc_num].length = length; in dwc2_hcd_urb_set_iso_desc_params()
725 return dwc2_urb->iso_descs[desc_num].status; in dwc2_hcd_urb_get_iso_desc_status()
731 return dwc2_urb->iso_descs[desc_num].actual_length; in dwc2_hcd_urb_get_iso_desc_actual_length()
737 struct dwc2_qh *qh = ep->hcpriv; in dwc2_hcd_is_bandwidth_allocated()
739 if (qh && !list_empty(&qh->qh_list_entry)) in dwc2_hcd_is_bandwidth_allocated()
748 struct dwc2_qh *qh = ep->hcpriv; in dwc2_hcd_get_ep_bandwidth()
755 return qh->host_us; in dwc2_hcd_get_ep_bandwidth()
765 * dwc2_handle_hcd_intr() - Called on every hardware interrupt
775 * dwc2_hcd_stop() - Halts the DWC_otg host mode operation
782 * dwc2_hcd_is_b_host() - Returns 1 if core currently is acting as B host,
790 * dwc2_hcd_dump_state() - Dumps hsotg state