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Searched refs:topckgen (Results 1 – 25 of 44) sorted by relevance

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/Linux-v6.1/Documentation/devicetree/bindings/sound/
Dmt2701-afe-pcm.txt69 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
70 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
71 <&topckgen CLK_TOP_AUD_48K_TIMING>,
72 <&topckgen CLK_TOP_AUD_44K_TIMING>,
73 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
74 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
75 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
76 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
77 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
78 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
[all …]
Dmtk-afe-pcm.txt26 <&topckgen TOP_AUDIO_SEL>,
27 <&topckgen TOP_AUD_INTBUS_SEL>,
28 <&topckgen TOP_APLL1_DIV0>,
29 <&topckgen TOP_APLL2_DIV0>,
30 <&topckgen TOP_I2S0_M_CK_SEL>,
31 <&topckgen TOP_I2S1_M_CK_SEL>,
32 <&topckgen TOP_I2S2_M_CK_SEL>,
33 <&topckgen TOP_I2S3_M_CK_SEL>,
34 <&topckgen TOP_I2S3_B_CK_SEL>;
Dmt6797-afe-pcm.txt29 <&topckgen CLK_TOP_MUX_AUDIO>,
30 <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
31 <&topckgen CLK_TOP_SYSPLL3_D4>,
32 <&topckgen CLK_TOP_SYSPLL1_D4>,
Dmt8183-afe-pcm.txt32 <&topckgen CLK_TOP_MUX_AUDIO>,
33 <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
34 <&topckgen CLK_TOP_SYSPLL_D2_D4>,
/Linux-v6.1/arch/arm64/boot/dts/mediatek/
Dmt8516.dtsi58 <&topckgen CLK_TOP_MAINPLL_D2>;
71 <&topckgen CLK_TOP_MAINPLL_D2>;
84 <&topckgen CLK_TOP_MAINPLL_D2>;
97 <&topckgen CLK_TOP_MAINPLL_D2>;
182 topckgen: topckgen@10000000 { label
183 compatible = "mediatek,mt8516-topckgen", "syscon";
218 clocks = <&topckgen CLK_TOP_CLK26M_D2>,
219 <&topckgen CLK_TOP_APXGPT>;
252 clocks = <&topckgen CLK_TOP_PMICWRAP_26M>,
253 <&topckgen CLK_TOP_PMICWRAP_AP>;
[all …]
Dmt8195.dtsi320 topckgen: syscon@10000000 { label
321 compatible = "mediatek,mt8195-topckgen", "syscon";
416 clocks = <&topckgen CLK_TOP_VPP>,
417 <&topckgen CLK_TOP_CAM>,
418 <&topckgen CLK_TOP_CCU>,
419 <&topckgen CLK_TOP_IMG>,
420 <&topckgen CLK_TOP_VENC>,
421 <&topckgen CLK_TOP_VDEC>,
422 <&topckgen CLK_TOP_WPE_VPP>,
423 <&topckgen CLK_TOP_CFG_VPP0>,
[all …]
Dmt8192.dtsi274 topckgen: syscon@10000000 { label
275 compatible = "mediatek,mt8192-topckgen", "syscon";
332 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
350 clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>;
392 clocks = <&topckgen CLK_TOP_DISP_SEL>,
406 clocks = <&topckgen CLK_TOP_IPE_SEL>,
419 clocks = <&topckgen CLK_TOP_IMG1_SEL>,
429 clocks = <&topckgen CLK_TOP_IMG2_SEL>,
439 clocks = <&topckgen CLK_TOP_MDP_SEL>,
448 clocks = <&topckgen CLK_TOP_VENC_SEL>,
[all …]
Dmt7622.dtsi250 clocks = <&topckgen CLK_TOP_HIF_SEL>;
259 <&topckgen CLK_TOP_AXI_SEL>;
292 topckgen: topckgen@10210000 { label
293 compatible = "mediatek,mt7622-topckgen",
332 clocks = <&topckgen CLK_TOP_RTC>;
396 clocks = <&topckgen CLK_TOP_UART_SEL>,
407 clocks = <&topckgen CLK_TOP_UART_SEL>,
418 clocks = <&topckgen CLK_TOP_UART_SEL>,
429 clocks = <&topckgen CLK_TOP_UART_SEL>,
439 clocks = <&topckgen CLK_TOP_PWM_SEL>,
[all …]
Dmt2712e.dtsi90 <&topckgen CLK_TOP_F_MP0_PLL1>;
103 <&topckgen CLK_TOP_F_MP0_PLL1>;
116 <&topckgen CLK_TOP_F_BIG_PLL1>;
246 topckgen: syscon@10000000 { label
247 compatible = "mediatek,mt2712-topckgen", "syscon";
285 clocks = <&topckgen CLK_TOP_MM_SEL>,
286 <&topckgen CLK_TOP_MFG_SEL>,
287 <&topckgen CLK_TOP_VENC_SEL>,
288 <&topckgen CLK_TOP_JPGDEC_SEL>,
289 <&topckgen CLK_TOP_A1SYS_HP_SEL>,
[all …]
Dmt7986a.dtsi115 topckgen: topckgen@1001b000 { label
116 compatible = "mediatek,mt7986-topckgen", "syscon";
188 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
190 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
191 <&topckgen CLK_TOP_UART_SEL>;
204 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
217 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
273 <&topckgen CLK_TOP_NETSYS_SEL>,
274 <&topckgen CLK_TOP_NETSYS_500M_SEL>;
281 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
[all …]
Dmt8173.dtsi349 topckgen: clock-controller@10000000 { label
350 compatible = "mediatek,mt8173-topckgen";
460 clocks = <&topckgen CLK_TOP_MM_SEL>;
466 clocks = <&topckgen CLK_TOP_MM_SEL>,
467 <&topckgen CLK_TOP_VENC_SEL>;
473 clocks = <&topckgen CLK_TOP_MM_SEL>;
479 clocks = <&topckgen CLK_TOP_MM_SEL>;
486 clocks = <&topckgen CLK_TOP_MM_SEL>,
487 <&topckgen CLK_TOP_VENC_LT_SEL>;
535 <&topckgen CLK_TOP_RTC_SEL>;
[all …]
Dmt8183.dtsi286 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
335 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
351 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
367 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
383 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
399 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
415 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
431 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
447 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
720 topckgen: syscon@10000000 { label
[all …]
Dmt8167.dtsi20 topckgen: topckgen@10000000 { label
21 compatible = "mediatek,mt8167-topckgen", "syscon";
51 clocks = <&topckgen CLK_TOP_SMI_MM>;
59 clocks = <&topckgen CLK_TOP_SMI_MM>,
60 <&topckgen CLK_TOP_RG_VDEC>;
67 clocks = <&topckgen CLK_TOP_SMI_MM>;
74 clocks = <&topckgen CLK_TOP_RG_AXI_MFG>,
75 <&topckgen CLK_TOP_RG_SLOW_MFG>;
Dmt8186.dtsi294 topckgen: syscon@10000000 { label
295 compatible = "mediatek,mt8186-topckgen", "syscon";
375 clocks = <&topckgen CLK_TOP_SPINOR>,
380 assigned-clocks = <&topckgen CLK_TOP_SPINOR>;
381 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>;
546 clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
547 <&topckgen CLK_TOP_SPI>,
558 clocks = <&topckgen CLK_TOP_DISP_PWM>,
570 clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
571 <&topckgen CLK_TOP_SPI>,
[all …]
Dmt6797.dtsi114 topckgen: topckgen@10000000 { label
115 compatible = "mediatek,mt6797-topckgen";
213 clocks = <&topckgen CLK_TOP_MUX_MFG>,
214 <&topckgen CLK_TOP_MUX_MM>,
215 <&topckgen CLK_TOP_MUX_VDEC>;
Dmt7622-rfb1.dts198 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
199 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
215 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
216 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
Dmt7622-bananapi-bpi-r64.dts225 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
226 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
242 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
243 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
/Linux-v6.1/arch/arm/boot/dts/
Dmt7629.dtsi98 clocks = <&topckgen CLK_TOP_HIF_SEL>;
100 assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
101 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
138 topckgen: syscon@10210000 { label
139 compatible = "mediatek,mt7629-topckgen", "syscon";
216 clocks = <&topckgen CLK_TOP_UART_SEL>,
227 clocks = <&topckgen CLK_TOP_UART_SEL>,
238 clocks = <&topckgen CLK_TOP_UART_SEL>,
248 clocks = <&topckgen CLK_TOP_PWM_SEL>,
252 assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
[all …]
Dmt2701.dtsi126 topckgen: syscon@10000000 { label
127 compatible = "mediatek,mt2701-topckgen", "syscon";
156 clocks = <&topckgen CLK_TOP_MM_SEL>,
157 <&topckgen CLK_TOP_MFG_SEL>,
158 <&topckgen CLK_TOP_ETHIF_SEL>;
343 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
344 <&topckgen CLK_TOP_SPI0_SEL>,
390 <&topckgen CLK_TOP_FLASH_SEL>;
403 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
404 <&topckgen CLK_TOP_SPI1_SEL>,
[all …]
Dmt7623.dtsi226 topckgen: syscon@10000000 { label
227 compatible = "mediatek,mt7623-topckgen",
228 "mediatek,mt2701-topckgen",
278 clocks = <&topckgen CLK_TOP_MM_SEL>,
279 <&topckgen CLK_TOP_MFG_SEL>,
280 <&topckgen CLK_TOP_ETHIF_SEL>;
424 clocks = <&topckgen CLK_TOP_PWM_SEL>,
488 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
489 <&topckgen CLK_TOP_SPI0_SEL>,
553 <&topckgen CLK_TOP_FLASH_SEL>;
[all …]
Dmt8135.dtsi127 topckgen: topckgen@10000000 { label
128 compatible = "mediatek,mt8135-topckgen";
Dmt7623a.dtsi34 clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
/Linux-v6.1/Documentation/devicetree/bindings/soc/mediatek/
Dscpsys.txt67 <&topckgen CLK_TOP_MM_SEL>;
68 <&topckgen CLK_TOP_VENC_SEL>,
69 <&topckgen CLK_TOP_VENC_LT_SEL>;
/Linux-v6.1/drivers/clk/mediatek/
DMakefile21 clk-mt6795-pericfg.o clk-mt6795-topckgen.o
56 obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
80 obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt8186-infra_ao.o \
98 obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195-apmixedsys.o clk-mt8195-topckgen.o \
/Linux-v6.1/Documentation/devicetree/bindings/rtc/
Drtc-mt7622.txt19 clocks = <&topckgen CLK_TOP_RTC>;

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