Lines Matching refs:topckgen
274 topckgen: syscon@10000000 { label
275 compatible = "mediatek,mt8192-topckgen", "syscon";
332 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
350 clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>;
392 clocks = <&topckgen CLK_TOP_DISP_SEL>,
406 clocks = <&topckgen CLK_TOP_IPE_SEL>,
419 clocks = <&topckgen CLK_TOP_IMG1_SEL>,
429 clocks = <&topckgen CLK_TOP_IMG2_SEL>,
439 clocks = <&topckgen CLK_TOP_MDP_SEL>,
448 clocks = <&topckgen CLK_TOP_VENC_SEL>,
457 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
480 clocks = <&topckgen CLK_TOP_CAM_SEL>,
534 clocks = <&topckgen CLK_TOP_CSW_F26M_D2>;
546 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
547 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
557 <&topckgen CLK_TOP_SPMI_MST_SEL>;
561 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
562 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
613 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
614 <&topckgen CLK_TOP_SPI_SEL>,
625 clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
638 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
639 <&topckgen CLK_TOP_SPI_SEL>,
652 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
653 <&topckgen CLK_TOP_SPI_SEL>,
666 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
667 <&topckgen CLK_TOP_SPI_SEL>,
680 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
681 <&topckgen CLK_TOP_SPI_SEL>,
694 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
695 <&topckgen CLK_TOP_SPI_SEL>,
708 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
709 <&topckgen CLK_TOP_SPI_SEL>,
722 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
723 <&topckgen CLK_TOP_SPI_SEL>,
751 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
752 <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
753 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
754 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
779 mediatek,topckgen = <&topckgen>;
803 <&topckgen CLK_TOP_AUDIO_SEL>,
804 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
805 <&topckgen CLK_TOP_MAINPLL_D4_D4>,
806 <&topckgen CLK_TOP_AUD_1_SEL>,
807 <&topckgen CLK_TOP_APLL1>,
808 <&topckgen CLK_TOP_AUD_2_SEL>,
809 <&topckgen CLK_TOP_APLL2>,
810 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
811 <&topckgen CLK_TOP_APLL1_D4>,
812 <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
813 <&topckgen CLK_TOP_APLL2_D4>,
814 <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
815 <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
816 <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
817 <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
818 <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
819 <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
820 <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
821 <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
822 <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
823 <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
824 <&topckgen CLK_TOP_APLL12_DIV0>,
825 <&topckgen CLK_TOP_APLL12_DIV1>,
826 <&topckgen CLK_TOP_APLL12_DIV2>,
827 <&topckgen CLK_TOP_APLL12_DIV3>,
828 <&topckgen CLK_TOP_APLL12_DIV4>,
829 <&topckgen CLK_TOP_APLL12_DIVB>,
830 <&topckgen CLK_TOP_APLL12_DIV5>,
831 <&topckgen CLK_TOP_APLL12_DIV6>,
832 <&topckgen CLK_TOP_APLL12_DIV7>,
833 <&topckgen CLK_TOP_APLL12_DIV8>,
834 <&topckgen CLK_TOP_APLL12_DIV9>,
835 <&topckgen CLK_TOP_AUDIO_H_SEL>,
911 assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
912 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>;
935 clocks = <&topckgen CLK_TOP_SFLASH_SEL>,
939 assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>;
1173 clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
1189 clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
1522 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
1523 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;