Lines Matching refs:topckgen
349 topckgen: clock-controller@10000000 { label
350 compatible = "mediatek,mt8173-topckgen";
460 clocks = <&topckgen CLK_TOP_MM_SEL>;
466 clocks = <&topckgen CLK_TOP_MM_SEL>,
467 <&topckgen CLK_TOP_VENC_SEL>;
473 clocks = <&topckgen CLK_TOP_MM_SEL>;
479 clocks = <&topckgen CLK_TOP_MM_SEL>;
486 clocks = <&topckgen CLK_TOP_MM_SEL>,
487 <&topckgen CLK_TOP_VENC_LT_SEL>;
535 <&topckgen CLK_TOP_RTC_SEL>;
563 clocks = <&topckgen CLK_TOP_SCP_SEL>;
762 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
763 <&topckgen CLK_TOP_SPI_SEL>,
786 assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>;
789 <&topckgen CLK_TOP_SPINFI_IFR_SEL>,
859 <&topckgen CLK_TOP_AUDIO_SEL>,
860 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
861 <&topckgen CLK_TOP_APLL1_DIV0>,
862 <&topckgen CLK_TOP_APLL2_DIV0>,
863 <&topckgen CLK_TOP_I2S0_M_SEL>,
864 <&topckgen CLK_TOP_I2S1_M_SEL>,
865 <&topckgen CLK_TOP_I2S2_M_SEL>,
866 <&topckgen CLK_TOP_I2S3_M_SEL>,
867 <&topckgen CLK_TOP_I2S3_B_SEL>;
878 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
879 <&topckgen CLK_TOP_AUD_2_SEL>;
880 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
881 <&topckgen CLK_TOP_APLL2>;
889 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
899 <&topckgen CLK_TOP_AXI_SEL>;
909 <&topckgen CLK_TOP_AXI_SEL>;
919 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
934 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
949 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
992 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
1322 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
1398 <&topckgen CLK_TOP_UNIVPLL_D2>,
1399 <&topckgen CLK_TOP_CCI400_SEL>,
1400 <&topckgen CLK_TOP_VDEC_SEL>,
1401 <&topckgen CLK_TOP_VCODECPLL>,
1403 <&topckgen CLK_TOP_VENC_LT_SEL>,
1404 <&topckgen CLK_TOP_VCODECPLL_370P5>;
1413 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
1414 <&topckgen CLK_TOP_CCI400_SEL>,
1415 <&topckgen CLK_TOP_VDEC_SEL>,
1418 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
1419 <&topckgen CLK_TOP_UNIVPLL_D2>,
1420 <&topckgen CLK_TOP_VCODECPLL>;
1466 clocks = <&topckgen CLK_TOP_VENC_SEL>;
1468 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
1469 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
1516 clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
1518 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
1520 <&topckgen CLK_TOP_VCODECPLL_370P5>;