Lines Matching refs:topckgen
320 topckgen: syscon@10000000 { label
321 compatible = "mediatek,mt8195-topckgen", "syscon";
416 clocks = <&topckgen CLK_TOP_VPP>,
417 <&topckgen CLK_TOP_CAM>,
418 <&topckgen CLK_TOP_CCU>,
419 <&topckgen CLK_TOP_IMG>,
420 <&topckgen CLK_TOP_VENC>,
421 <&topckgen CLK_TOP_VDEC>,
422 <&topckgen CLK_TOP_WPE_VPP>,
423 <&topckgen CLK_TOP_CFG_VPP0>,
472 clocks = <&topckgen CLK_TOP_CFG_VDO0>,
489 clocks = <&topckgen CLK_TOP_CFG_VPP1>,
534 clocks = <&topckgen CLK_TOP_CFG_VDO1>,
559 clocks = <&topckgen CLK_TOP_HDMI_APB>;
582 clocks = <&topckgen CLK_TOP_IPE>,
647 clocks = <&topckgen CLK_TOP_SENINF>,
648 <&topckgen CLK_TOP_SENINF2>;
662 clocks = <&topckgen CLK_TOP_ADSP>,
663 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>;
672 clocks = <&topckgen CLK_TOP_A1SYS_HP>,
673 <&topckgen CLK_TOP_AUD_INTBUS>,
674 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
704 clocks = <&topckgen CLK_TOP_CLK26M_D2>;
715 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
716 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
726 <&topckgen CLK_TOP_SPMI_M_MST>;
730 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
731 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
782 clocks = <&topckgen CLK_TOP_ADSP>,
784 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
785 <&topckgen CLK_TOP_MAINPLL_D7_D2>,
787 <&topckgen CLK_TOP_AUDIO_H>;
817 mediatek,topckgen = <&topckgen>;
825 <&topckgen CLK_TOP_APLL12_DIV0>,
826 <&topckgen CLK_TOP_APLL12_DIV1>,
827 <&topckgen CLK_TOP_APLL12_DIV2>,
828 <&topckgen CLK_TOP_APLL12_DIV3>,
829 <&topckgen CLK_TOP_APLL12_DIV9>,
830 <&topckgen CLK_TOP_A1SYS_HP>,
831 <&topckgen CLK_TOP_AUD_INTBUS>,
832 <&topckgen CLK_TOP_AUDIO_H>,
833 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
834 <&topckgen CLK_TOP_DPTX_MCK>,
835 <&topckgen CLK_TOP_I2SO1_MCK>,
836 <&topckgen CLK_TOP_I2SO2_MCK>,
837 <&topckgen CLK_TOP_I2SI1_MCK>,
838 <&topckgen CLK_TOP_I2SI2_MCK>,
946 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
947 <&topckgen CLK_TOP_SPI>,
960 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
961 <&topckgen CLK_TOP_SPI>,
974 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
975 <&topckgen CLK_TOP_SPI>,
988 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
989 <&topckgen CLK_TOP_SPI>,
1002 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1003 <&topckgen CLK_TOP_SPI>,
1016 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1017 <&topckgen CLK_TOP_SPI>,
1029 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1030 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1040 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1041 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1054 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
1055 <&topckgen CLK_TOP_SSUSB_XHCI>;
1056 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1057 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1059 <&topckgen CLK_TOP_SSUSB_REF>,
1076 clocks = <&topckgen CLK_TOP_MSDC50_0>,
1089 clocks = <&topckgen CLK_TOP_MSDC30_1>,
1093 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1094 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1104 clocks = <&topckgen CLK_TOP_MSDC30_2>,
1108 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
1109 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1121 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
1122 <&topckgen CLK_TOP_SSUSB_XHCI_1P>;
1123 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1124 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1126 <&topckgen CLK_TOP_SSUSB_P1_REF>,
1145 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>,
1146 <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
1147 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1148 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1150 <&topckgen CLK_TOP_SSUSB_P2_REF>,
1169 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>,
1170 <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
1171 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1172 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1174 <&topckgen CLK_TOP_SSUSB_P3_REF>,
1190 clocks = <&topckgen CLK_TOP_SPINOR>,
1255 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>;
1270 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>;
1417 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>,
1426 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>;
1445 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>,
1454 <&topckgen CLK_TOP_SSUSB_PHY_REF>;