Lines Matching refs:topckgen
286 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
335 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
351 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
367 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
383 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
399 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
415 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
431 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
447 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
720 topckgen: syscon@10000000 { label
721 compatible = "mediatek,mt8183-topckgen", "syscon";
777 clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
792 clocks = <&topckgen CLK_TOP_MUX_MFG>;
824 clocks = <&topckgen CLK_TOP_MUX_MM>,
846 clocks = <&topckgen CLK_TOP_MUX_CAM>,
864 clocks = <&topckgen CLK_TOP_MUX_IMG>,
887 clocks = <&topckgen CLK_TOP_MUX_IPU_IF>,
888 <&topckgen CLK_TOP_MUX_DSP>,
905 clocks = <&topckgen CLK_TOP_MUX_DSP1>;
913 clocks = <&topckgen CLK_TOP_MUX_DSP2>;
940 clocks = <&topckgen CLK_TOP_MUX_PMICSPI>,
971 clocks = <&topckgen CLK_TOP_CLK13M>;
1097 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1098 <&topckgen CLK_TOP_MUX_SPI>,
1258 clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>,
1297 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1298 <&topckgen CLK_TOP_MUX_SPI>,
1324 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1325 <&topckgen CLK_TOP_MUX_SPI>,
1337 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1338 <&topckgen CLK_TOP_MUX_SPI>,
1410 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1411 <&topckgen CLK_TOP_MUX_SPI>,
1423 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1424 <&topckgen CLK_TOP_MUX_SPI>,
1516 <&topckgen CLK_TOP_MUX_AUDIO>,
1517 <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
1518 <&topckgen CLK_TOP_SYSPLL_D2_D4>,
1519 <&topckgen CLK_TOP_MUX_AUD_1>,
1520 <&topckgen CLK_TOP_APLL1_CK>,
1521 <&topckgen CLK_TOP_MUX_AUD_2>,
1522 <&topckgen CLK_TOP_APLL2_CK>,
1523 <&topckgen CLK_TOP_MUX_AUD_ENG1>,
1524 <&topckgen CLK_TOP_APLL1_D8>,
1525 <&topckgen CLK_TOP_MUX_AUD_ENG2>,
1526 <&topckgen CLK_TOP_APLL2_D8>,
1527 <&topckgen CLK_TOP_MUX_APLL_I2S0>,
1528 <&topckgen CLK_TOP_MUX_APLL_I2S1>,
1529 <&topckgen CLK_TOP_MUX_APLL_I2S2>,
1530 <&topckgen CLK_TOP_MUX_APLL_I2S3>,
1531 <&topckgen CLK_TOP_MUX_APLL_I2S4>,
1532 <&topckgen CLK_TOP_MUX_APLL_I2S5>,
1533 <&topckgen CLK_TOP_APLL12_DIV0>,
1534 <&topckgen CLK_TOP_APLL12_DIV1>,
1535 <&topckgen CLK_TOP_APLL12_DIV2>,
1536 <&topckgen CLK_TOP_APLL12_DIV3>,
1537 <&topckgen CLK_TOP_APLL12_DIV4>,
1538 <&topckgen CLK_TOP_APLL12_DIVB>,
1539 /*<&topckgen CLK_TOP_APLL12_DIV5>,*/
1591 clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>,
1603 clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>,
1681 clocks = <&topckgen CLK_TOP_MFGPLL_CK>;