| /Linux-v5.4/arch/alpha/lib/ |
| D | fpreg.c | 12 #define STT(reg,val) asm volatile ("ftoit $f"#reg",%0" : "=r"(val)); argument
14 #define STT(reg,val) asm volatile ("stt $f"#reg",%0" : "=m"(val)); argument
20 unsigned long val; in alpha_read_fp_reg() local
23 case 0: STT( 0, val); break; in alpha_read_fp_reg()
24 case 1: STT( 1, val); break; in alpha_read_fp_reg()
25 case 2: STT( 2, val); break; in alpha_read_fp_reg()
26 case 3: STT( 3, val); break; in alpha_read_fp_reg()
27 case 4: STT( 4, val); break; in alpha_read_fp_reg()
28 case 5: STT( 5, val); break; in alpha_read_fp_reg()
29 case 6: STT( 6, val); break; in alpha_read_fp_reg()
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| /Linux-v5.4/drivers/media/tuners/ |
| D | tda18271-maps.c | 19 u8 val; member
190 { .rfmax = 62000, .val = 0x00 },
191 { .rfmax = 84000, .val = 0x01 },
192 { .rfmax = 100000, .val = 0x02 },
193 { .rfmax = 140000, .val = 0x03 },
194 { .rfmax = 170000, .val = 0x04 },
195 { .rfmax = 180000, .val = 0x05 },
196 { .rfmax = 865000, .val = 0x06 },
197 { .rfmax = 0, .val = 0x00 }, /* end */
201 { .rfmax = 61100, .val = 0x74 },
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| /Linux-v5.4/drivers/hwtracing/coresight/ |
| D | coresight-etm-cp14.c | 15 int etm_readl_cp14(u32 reg, unsigned int *val) in etm_readl_cp14() argument
19 *val = etm_read(ETMCR); in etm_readl_cp14()
22 *val = etm_read(ETMCCR); in etm_readl_cp14()
25 *val = etm_read(ETMTRIGGER); in etm_readl_cp14()
28 *val = etm_read(ETMSR); in etm_readl_cp14()
31 *val = etm_read(ETMSCR); in etm_readl_cp14()
34 *val = etm_read(ETMTSSCR); in etm_readl_cp14()
37 *val = etm_read(ETMTEEVR); in etm_readl_cp14()
40 *val = etm_read(ETMTECR1); in etm_readl_cp14()
43 *val = etm_read(ETMFFLR); in etm_readl_cp14()
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| /Linux-v5.4/drivers/net/ethernet/neterion/vxge/ |
| D | vxge-reg.h | 25 #define vxge_vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz))) argument
26 #define vxge_vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz))) argument
54 #define VXGE_EPROM_IMG_MAJOR(val) (u32) vxge_bVALn(val, 48, 4) argument
55 #define VXGE_EPROM_IMG_MINOR(val) (u32) vxge_bVALn(val, 52, 4) argument
56 #define VXGE_EPROM_IMG_FIX(val) (u32) vxge_bVALn(val, 56, 4) argument
57 #define VXGE_EPROM_IMG_BUILD(val) (u32) vxge_bVALn(val, 60, 4) argument
59 #define VXGE_HW_GET_EPROM_IMAGE_INDEX(val) vxge_bVALn(val, 16, 8) argument
60 #define VXGE_HW_GET_EPROM_IMAGE_VALID(val) vxge_bVALn(val, 31, 1) argument
61 #define VXGE_HW_GET_EPROM_IMAGE_TYPE(val) vxge_bVALn(val, 40, 8) argument
62 #define VXGE_HW_GET_EPROM_IMAGE_REV(val) vxge_bVALn(val, 48, 16) argument
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| /Linux-v5.4/arch/arm/include/asm/hardware/ |
| D | cp14.h | 12 #define dbg_write(val, reg) WCP14_##reg(val) argument
14 #define etm_write(val, reg) WCP14_##reg(val) argument
19 u32 val; \
20 asm volatile("mrc p14, "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val)); \
21 val; \
24 #define MCR14(val, op1, crn, crm, op2) \ argument
26 asm volatile("mcr p14, "#op1", %0, "#crn", "#crm", "#op2 : : "r" (val));\
152 #define WCP14_DBGDTRTXint(val) MCR14(val, 0, c0, c5, 0) argument
153 #define WCP14_DBGWFAR(val) MCR14(val, 0, c0, c6, 0) argument
154 #define WCP14_DBGVCR(val) MCR14(val, 0, c0, c7, 0) argument
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| /Linux-v5.4/drivers/net/wireless/broadcom/brcm80211/brcmsmac/ |
| D | types.h | 133 #define CONF_HAS(config, val) ((config) & (1 << (val))) argument
138 #define CONF_IS(config, val) ((config) == (1 << (val))) argument
139 #define CONF_GE(config, val) ((config) & (0-(1 << (val)))) argument
140 #define CONF_GT(config, val) ((config) & (0-2*(1 << (val)))) argument
141 #define CONF_LT(config, val) ((config) & ((1 << (val))-1)) argument
142 #define CONF_LE(config, val) ((config) & (2*(1 << (val))-1)) argument
146 #define NCONF_HAS(val) CONF_HAS(NCONF, val) argument
148 #define NCONF_IS(val) CONF_IS(NCONF, val) argument
149 #define NCONF_GE(val) CONF_GE(NCONF, val) argument
150 #define NCONF_GT(val) CONF_GT(NCONF, val) argument
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| /Linux-v5.4/drivers/gpu/drm/msm/adreno/ |
| D | a2xx.xml.h | 316 static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR() argument
318 …return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHA… in A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR()
322 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR() argument
324 …return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHA… in A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR()
328 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR() argument
330 …return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BE… in A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR()
334 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR() argument
336 …return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BE… in A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR()
340 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR() argument
342 …return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BE… in A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR()
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| D | adreno_pm4.xml.h | 380 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) in CP_LOAD_STATE_0_DST_OFF() argument
382 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK; in CP_LOAD_STATE_0_DST_OFF()
386 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) in CP_LOAD_STATE_0_STATE_SRC() argument
388 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK; in CP_LOAD_STATE_0_STATE_SRC()
392 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) in CP_LOAD_STATE_0_STATE_BLOCK() argument
394 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK; in CP_LOAD_STATE_0_STATE_BLOCK()
398 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) in CP_LOAD_STATE_0_NUM_UNIT() argument
400 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK; in CP_LOAD_STATE_0_NUM_UNIT()
406 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) in CP_LOAD_STATE_1_STATE_TYPE() argument
408 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK; in CP_LOAD_STATE_1_STATE_TYPE()
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| D | a3xx.xml.h | 946 static inline uint32_t A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(uint32_t val) in A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES() argument
948 …return ((val) << A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT) & A3XX_GRAS_CL_CLIP_CNTL_NUM_… in A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES()
954 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) in A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ() argument
956 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; in A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ()
960 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) in A3XX_GRAS_CL_GB_CLIP_ADJ_VERT() argument
962 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; in A3XX_GRAS_CL_GB_CLIP_ADJ_VERT()
968 static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val) in A3XX_GRAS_CL_VPORT_XOFFSET() argument
970 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK; in A3XX_GRAS_CL_VPORT_XOFFSET()
976 static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val) in A3XX_GRAS_CL_VPORT_XSCALE() argument
978 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_XSCALE__MASK; in A3XX_GRAS_CL_VPORT_XSCALE()
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| D | a4xx.xml.h | 847 static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) in A4XX_CGC_HLSQ_EARLY_CYC() argument
849 return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK; in A4XX_CGC_HLSQ_EARLY_CYC()
904 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) in A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH() argument
906 …return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WID… in A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH()
910 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) in A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT() argument
912 …return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HE… in A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT()
926 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) in A4XX_RB_MODE_CONTROL_WIDTH() argument
928 return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK; in A4XX_RB_MODE_CONTROL_WIDTH()
932 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) in A4XX_RB_MODE_CONTROL_HEIGHT() argument
934 return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK; in A4XX_RB_MODE_CONTROL_HEIGHT()
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| D | a6xx.xml.h | 1073 static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) in A6XX_CP_PROTECT_REG_BASE_ADDR() argument
1075 return ((val) << A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A6XX_CP_PROTECT_REG_BASE_ADDR__MASK; in A6XX_CP_PROTECT_REG_BASE_ADDR()
1079 static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) in A6XX_CP_PROTECT_REG_MASK_LEN() argument
1081 return ((val) << A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A6XX_CP_PROTECT_REG_MASK_LEN__MASK; in A6XX_CP_PROTECT_REG_MASK_LEN()
2004 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val) in A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX() argument
2006 …return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_I… in A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX()
2010 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val) in A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL() argument
2012 …return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING… in A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL()
2018 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) in A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN() argument
2020 …return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__… in A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN()
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| D | a5xx.xml.h | 1045 static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) in A5XX_CP_PROTECT_REG_BASE_ADDR() argument
1047 return ((val) << A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A5XX_CP_PROTECT_REG_BASE_ADDR__MASK; in A5XX_CP_PROTECT_REG_BASE_ADDR()
1051 static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) in A5XX_CP_PROTECT_REG_MASK_LEN() argument
1053 return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK; in A5XX_CP_PROTECT_REG_MASK_LEN()
1958 static inline uint32_t A5XX_VSC_BIN_SIZE_WIDTH(uint32_t val) in A5XX_VSC_BIN_SIZE_WIDTH() argument
1960 return ((val >> 5) << A5XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A5XX_VSC_BIN_SIZE_WIDTH__MASK; in A5XX_VSC_BIN_SIZE_WIDTH()
1964 static inline uint32_t A5XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) in A5XX_VSC_BIN_SIZE_HEIGHT() argument
1966 return ((val >> 5) << A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A5XX_VSC_BIN_SIZE_HEIGHT__MASK; in A5XX_VSC_BIN_SIZE_HEIGHT()
1982 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) in A5XX_VSC_PIPE_CONFIG_REG_X() argument
1984 return ((val) << A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_X__MASK; in A5XX_VSC_PIPE_CONFIG_REG_X()
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| /Linux-v5.4/drivers/phy/ |
| D | phy-xgene.c | 554 u32 val; in sds_wr() local
564 val = readl(csr_base + indirect_cmd_reg); in sds_wr()
565 } while (!(val & CFG_IND_CMD_DONE_MASK) && in sds_wr()
567 if (!(val & CFG_IND_CMD_DONE_MASK)) in sds_wr()
576 u32 val; in sds_rd() local
584 val = readl(csr_base + indirect_cmd_reg); in sds_rd()
585 } while (!(val & CFG_IND_CMD_DONE_MASK) && in sds_rd()
588 if (!(val & CFG_IND_CMD_DONE_MASK)) in sds_rd()
597 u32 val; in cmu_wr() local
606 SATA_ENET_SDS_IND_RDATA_REG, reg, &val); in cmu_wr()
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| /Linux-v5.4/arch/mips/include/asm/ |
| D | mipsregs.h | 1319 #define write_r10k_perf_cntr(counter,val) \ argument
1324 : "r" (val), "i" (counter)); \
1338 #define write_r10k_perf_cntl(counter,val) \ argument
1343 : "r" (val), "i" (counter)); \
1445 #define __write_ulong_c0_register(reg, sel, val) \ argument
1448 __write_32bit_c0_register(reg, sel, val); \
1450 __write_64bit_c0_register(reg, sel, val); \
1504 #define __write_64bit_c0_split(source, sel, val) \ argument
1506 unsigned long long __tmp = (val); \
1583 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) argument
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| /Linux-v5.4/arch/mips/pci/ |
| D | pci-bcm63xx.c | 109 static void bcm63xx_int_cfg_writel(u32 val, u32 reg) in bcm63xx_int_cfg_writel() argument
116 bcm_mpi_writel(val, MPI_PCICFGDATA_REG); in bcm63xx_int_cfg_writel()
123 u32 val; in bcm63xx_reset_pcie() local
132 val = bcm_misc_readl(reg); in bcm63xx_reset_pcie()
133 val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN; in bcm63xx_reset_pcie()
134 bcm_misc_writel(val, reg); in bcm63xx_reset_pcie()
152 u32 val; in bcm63xx_register_pcie() local
164 val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG); in bcm63xx_register_pcie()
165 val |= OPT1_RD_BE_OPT_EN; in bcm63xx_register_pcie()
166 val |= OPT1_RD_REPLY_BE_FIX_EN; in bcm63xx_register_pcie()
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| /Linux-v5.4/drivers/net/ethernet/chelsio/cxgb4/ |
| D | cxgb4_tc_u32_parse.h | 41 int (*val)(struct ch_filter_specification *f, u32 val, u32 mask); member
46 u32 val, u32 mask) in cxgb4_fill_ipv4_tos() argument
48 f->val.tos = (ntohl(val) >> 16) & 0x000000FF; in cxgb4_fill_ipv4_tos()
55 u32 val, u32 mask) in cxgb4_fill_ipv4_frag() argument
60 frag_val = (ntohl(val) >> 13) & 0x00000007; in cxgb4_fill_ipv4_frag()
64 f->val.frag = 1; in cxgb4_fill_ipv4_frag()
67 f->val.frag = 0; in cxgb4_fill_ipv4_frag()
77 u32 val, u32 mask) in cxgb4_fill_ipv4_proto() argument
79 f->val.proto = (ntohl(val) >> 16) & 0x000000FF; in cxgb4_fill_ipv4_proto()
86 u32 val, u32 mask) in cxgb4_fill_ipv4_src_ip() argument
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| /Linux-v5.4/sound/pci/ac97/ |
| D | ac97_proc.c | 95 unsigned short val, tmp, ext, mext; in snd_ac97_proc_read_main() local
115 val = snd_ac97_read(ac97, AC97_INT_PAGING); in snd_ac97_proc_read_main()
126 AC97_PAGE_MASK, val & AC97_PAGE_MASK); in snd_ac97_proc_read_main()
130 val = ac97->caps; in snd_ac97_proc_read_main()
132 val & AC97_BC_DEDICATED_MIC ? " -dedicated MIC PCM IN channel-" : "", in snd_ac97_proc_read_main()
133 val & AC97_BC_RESERVED1 ? " -reserved1-" : "", in snd_ac97_proc_read_main()
134 val & AC97_BC_BASS_TREBLE ? " -bass & treble-" : "", in snd_ac97_proc_read_main()
135 val & AC97_BC_SIM_STEREO ? " -simulated stereo-" : "", in snd_ac97_proc_read_main()
136 val & AC97_BC_HEADPHONE ? " -headphone out-" : "", in snd_ac97_proc_read_main()
137 val & AC97_BC_LOUDNESS ? " -loudness-" : ""); in snd_ac97_proc_read_main()
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| /Linux-v5.4/drivers/net/wireless/ath/ath5k/ |
| D | eeprom.c | 43 u16 val; in ath5k_eeprom_bin2freq() local
50 val = (5 * bin) + 4800; in ath5k_eeprom_bin2freq()
52 val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 : in ath5k_eeprom_bin2freq()
56 val = bin + 2300; in ath5k_eeprom_bin2freq()
58 val = bin + 2400; in ath5k_eeprom_bin2freq()
61 return val; in ath5k_eeprom_bin2freq()
76 u16 val; in ath5k_eeprom_init_header() local
96 AR5K_EEPROM_READ(AR5K_EEPROM_SIZE_UPPER, val); in ath5k_eeprom_init_header()
97 if (val) { in ath5k_eeprom_init_header()
98 eep_max = (val & AR5K_EEPROM_SIZE_UPPER_MASK) << in ath5k_eeprom_init_header()
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| /Linux-v5.4/drivers/gpu/drm/msm/dsi/ |
| D | dsi.xml.h | 113 static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val) in DSI_6G_HW_VERSION_MAJOR() argument
115 return ((val) << DSI_6G_HW_VERSION_MAJOR__SHIFT) & DSI_6G_HW_VERSION_MAJOR__MASK; in DSI_6G_HW_VERSION_MAJOR()
119 static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val) in DSI_6G_HW_VERSION_MINOR() argument
121 return ((val) << DSI_6G_HW_VERSION_MINOR__SHIFT) & DSI_6G_HW_VERSION_MINOR__MASK; in DSI_6G_HW_VERSION_MINOR()
125 static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val) in DSI_6G_HW_VERSION_STEP() argument
127 return ((val) << DSI_6G_HW_VERSION_STEP__SHIFT) & DSI_6G_HW_VERSION_STEP__MASK; in DSI_6G_HW_VERSION_STEP()
156 static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val) in DSI_VID_CFG0_VIRT_CHANNEL() argument
158 return ((val) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT) & DSI_VID_CFG0_VIRT_CHANNEL__MASK; in DSI_VID_CFG0_VIRT_CHANNEL()
162 static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val) in DSI_VID_CFG0_DST_FORMAT() argument
164 return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK; in DSI_VID_CFG0_DST_FORMAT()
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| /Linux-v5.4/drivers/gpu/drm/i915/ |
| D | i915_fixed.h | 15 u32 val; member
18 #define FP_16_16_MAX ((uint_fixed_16_16_t){ .val = UINT_MAX })
20 static inline bool is_fixed16_zero(uint_fixed_16_16_t val) in is_fixed16_zero() argument
22 return val.val == 0; in is_fixed16_zero()
25 static inline uint_fixed_16_16_t u32_to_fixed16(u32 val) in u32_to_fixed16() argument
27 uint_fixed_16_16_t fp = { .val = val << 16 }; in u32_to_fixed16()
29 WARN_ON(val > U16_MAX); in u32_to_fixed16()
36 return DIV_ROUND_UP(fp.val, 1 << 16); in fixed16_to_u32_round_up()
41 return fp.val >> 16; in fixed16_to_u32()
47 uint_fixed_16_16_t min = { .val = min(min1.val, min2.val) }; in min_fixed16()
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| /Linux-v5.4/drivers/hwmon/ |
| D | hwmon-vid.c | 69 int vid_from_reg(int val, u8 vrm) in vid_from_reg() argument
77 val &= 0x3f; in vid_from_reg()
78 if ((val & 0x1f) == 0x1f) in vid_from_reg()
80 if ((val & 0x1f) <= 0x09 || val == 0x0a) in vid_from_reg()
81 vid = 1087500 - (val & 0x1f) * 25000; in vid_from_reg()
83 vid = 1862500 - (val & 0x1f) * 25000; in vid_from_reg()
84 if (val & 0x20) in vid_from_reg()
90 val &= 0xff; in vid_from_reg()
91 if (val < 0x02 || val > 0xb2) in vid_from_reg()
93 return (1600000 - (val - 2) * 6250 + 500) / 1000; in vid_from_reg()
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| /Linux-v5.4/drivers/net/phy/ |
| D | bcm-phy-lib.c | 17 int bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val) in bcm_phy_write_exp() argument
25 return phy_write(phydev, MII_BCM54XX_EXP_DATA, val); in bcm_phy_write_exp()
31 int val; in bcm_phy_read_exp() local
33 val = phy_write(phydev, MII_BCM54XX_EXP_SEL, reg); in bcm_phy_read_exp()
34 if (val < 0) in bcm_phy_read_exp()
35 return val; in bcm_phy_read_exp()
37 val = phy_read(phydev, MII_BCM54XX_EXP_DATA); in bcm_phy_read_exp()
42 return val; in bcm_phy_read_exp()
57 int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val) in bcm54xx_auxctl_write() argument
59 return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val); in bcm54xx_auxctl_write()
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| /Linux-v5.4/drivers/gpu/drm/msm/disp/mdp4/ |
| D | mdp4.xml.h | 113 static inline uint32_t MDP4_VERSION_MINOR(uint32_t val) in MDP4_VERSION_MINOR() argument
115 return ((val) << MDP4_VERSION_MINOR__SHIFT) & MDP4_VERSION_MINOR__MASK; in MDP4_VERSION_MINOR()
119 static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val) in MDP4_VERSION_MAJOR() argument
121 return ((val) << MDP4_VERSION_MAJOR__SHIFT) & MDP4_VERSION_MAJOR__MASK; in MDP4_VERSION_MAJOR()
141 static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_PRIM() argument
143 return ((val) << MDP4_DISP_INTF_SEL_PRIM__SHIFT) & MDP4_DISP_INTF_SEL_PRIM__MASK; in MDP4_DISP_INTF_SEL_PRIM()
147 static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_SEC() argument
149 return ((val) << MDP4_DISP_INTF_SEL_SEC__SHIFT) & MDP4_DISP_INTF_SEL_SEC__MASK; in MDP4_DISP_INTF_SEL_SEC()
153 static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_EXT() argument
155 return ((val) << MDP4_DISP_INTF_SEL_EXT__SHIFT) & MDP4_DISP_INTF_SEL_EXT__MASK; in MDP4_DISP_INTF_SEL_EXT()
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| /Linux-v5.4/drivers/gpu/drm/msm/disp/mdp5/ |
| D | mdp5.xml.h | 180 static inline uint32_t MDSS_HW_VERSION_STEP(uint32_t val) in MDSS_HW_VERSION_STEP() argument
182 return ((val) << MDSS_HW_VERSION_STEP__SHIFT) & MDSS_HW_VERSION_STEP__MASK; in MDSS_HW_VERSION_STEP()
186 static inline uint32_t MDSS_HW_VERSION_MINOR(uint32_t val) in MDSS_HW_VERSION_MINOR() argument
188 return ((val) << MDSS_HW_VERSION_MINOR__SHIFT) & MDSS_HW_VERSION_MINOR__MASK; in MDSS_HW_VERSION_MINOR()
192 static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val) in MDSS_HW_VERSION_MAJOR() argument
194 return ((val) << MDSS_HW_VERSION_MAJOR__SHIFT) & MDSS_HW_VERSION_MAJOR__MASK; in MDSS_HW_VERSION_MAJOR()
207 static inline uint32_t MDP5_HW_VERSION_STEP(uint32_t val) in MDP5_HW_VERSION_STEP() argument
209 return ((val) << MDP5_HW_VERSION_STEP__SHIFT) & MDP5_HW_VERSION_STEP__MASK; in MDP5_HW_VERSION_STEP()
213 static inline uint32_t MDP5_HW_VERSION_MINOR(uint32_t val) in MDP5_HW_VERSION_MINOR() argument
215 return ((val) << MDP5_HW_VERSION_MINOR__SHIFT) & MDP5_HW_VERSION_MINOR__MASK; in MDP5_HW_VERSION_MINOR()
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| /Linux-v5.4/drivers/gpu/drm/i915/display/ |
| D | intel_dpio_phy.c | 271 u32 val; in bxt_ddi_phy_set_signal_level() local
281 val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch)); in bxt_ddi_phy_set_signal_level()
282 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT); in bxt_ddi_phy_set_signal_level()
283 I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
285 val = I915_READ(BXT_PORT_TX_DW2_LN0(phy, ch)); in bxt_ddi_phy_set_signal_level()
286 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE); in bxt_ddi_phy_set_signal_level()
287 val |= margin << MARGIN_000_SHIFT | scale << UNIQ_TRANS_SCALE_SHIFT; in bxt_ddi_phy_set_signal_level()
288 I915_WRITE(BXT_PORT_TX_DW2_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
290 val = I915_READ(BXT_PORT_TX_DW3_LN0(phy, ch)); in bxt_ddi_phy_set_signal_level()
291 val &= ~SCALE_DCOMP_METHOD; in bxt_ddi_phy_set_signal_level()
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