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/Linux-v5.4/arch/powerpc/perf/
Dgeneric-compat-pmu.c97 #define C(x) PERF_COUNT_HW_CACHE_##x macro
104 static int generic_compat_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
105 [ C(L1D) ] = {
106 [ C(OP_READ) ] = {
107 [ C(RESULT_ACCESS) ] = 0,
108 [ C(RESULT_MISS) ] = 0,
110 [ C(OP_WRITE) ] = {
111 [ C(RESULT_ACCESS) ] = 0,
112 [ C(RESULT_MISS) ] = 0,
114 [ C(OP_PREFETCH) ] = {
[all …]
Dpower8-pmu.c249 #define C(x) PERF_COUNT_HW_CACHE_##x macro
256 static int power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
257 [ C(L1D) ] = {
258 [ C(OP_READ) ] = {
259 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
260 [ C(RESULT_MISS) ] = PM_LD_MISS_L1,
262 [ C(OP_WRITE) ] = {
263 [ C(RESULT_ACCESS) ] = 0,
264 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
266 [ C(OP_PREFETCH) ] = {
[all …]
Dpower9-pmu.c306 #define C(x) PERF_COUNT_HW_CACHE_##x macro
313 static int power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
314 [ C(L1D) ] = {
315 [ C(OP_READ) ] = {
316 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
317 [ C(RESULT_MISS) ] = PM_LD_MISS_L1_FIN,
319 [ C(OP_WRITE) ] = {
320 [ C(RESULT_ACCESS) ] = 0,
321 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
323 [ C(OP_PREFETCH) ] = {
[all …]
De6500-pmu.c28 #define C(x) PERF_COUNT_HW_CACHE_##x macro
35 static int e6500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
36 [C(L1D)] = {
38 [C(OP_READ)] = { 27, 222 },
39 [C(OP_WRITE)] = { 28, 223 },
40 [C(OP_PREFETCH)] = { 29, 0 },
42 [C(L1I)] = {
44 [C(OP_READ)] = { 2, 254 },
45 [C(OP_WRITE)] = { -1, -1 },
46 [C(OP_PREFETCH)] = { 37, 0 },
[all …]
De500-pmu.c27 #define C(x) PERF_COUNT_HW_CACHE_##x macro
34 static int e500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
39 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
40 [C(OP_READ)] = { 27, 0 },
41 [C(OP_WRITE)] = { 28, 0 },
42 [C(OP_PREFETCH)] = { 29, 0 },
44 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
45 [C(OP_READ)] = { 2, 60 },
46 [C(OP_WRITE)] = { -1, -1 },
47 [C(OP_PREFETCH)] = { 0, 0 },
[all …]
/Linux-v5.4/arch/arc/include/asm/
Dperf_event.h123 #define C(_x) PERF_COUNT_HW_CACHE_##_x macro
126 static const unsigned arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
127 [C(L1D)] = {
128 [C(OP_READ)] = {
129 [C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC,
130 [C(RESULT_MISS)] = PERF_COUNT_ARC_DCLM,
132 [C(OP_WRITE)] = {
133 [C(RESULT_ACCESS)] = PERF_COUNT_ARC_STC,
134 [C(RESULT_MISS)] = PERF_COUNT_ARC_DCSM,
136 [C(OP_PREFETCH)] = {
[all …]
/Linux-v5.4/arch/sh/kernel/cpu/sh4/
Dperf_event.c84 #define C(x) PERF_COUNT_HW_CACHE_##x macro
91 [ C(L1D) ] = {
92 [ C(OP_READ) ] = {
93 [ C(RESULT_ACCESS) ] = 0x0001,
94 [ C(RESULT_MISS) ] = 0x0004,
96 [ C(OP_WRITE) ] = {
97 [ C(RESULT_ACCESS) ] = 0x0002,
98 [ C(RESULT_MISS) ] = 0x0005,
100 [ C(OP_PREFETCH) ] = {
101 [ C(RESULT_ACCESS) ] = 0,
[all …]
/Linux-v5.4/arch/sh/kernel/cpu/sh4a/
Dperf_event.c109 #define C(x) PERF_COUNT_HW_CACHE_##x macro
116 [ C(L1D) ] = {
117 [ C(OP_READ) ] = {
118 [ C(RESULT_ACCESS) ] = 0x0031,
119 [ C(RESULT_MISS) ] = 0x0032,
121 [ C(OP_WRITE) ] = {
122 [ C(RESULT_ACCESS) ] = 0x0039,
123 [ C(RESULT_MISS) ] = 0x003a,
125 [ C(OP_PREFETCH) ] = {
126 [ C(RESULT_ACCESS) ] = 0,
[all …]
/Linux-v5.4/arch/x86/events/intel/
Dp6.c28 [ C(L1D) ] = {
29 [ C(OP_READ) ] = {
30 [ C(RESULT_ACCESS) ] = 0x0043, /* DATA_MEM_REFS */
31 [ C(RESULT_MISS) ] = 0x0045, /* DCU_LINES_IN */
33 [ C(OP_WRITE) ] = {
34 [ C(RESULT_ACCESS) ] = 0,
35 [ C(RESULT_MISS) ] = 0x0f29, /* L2_LD:M:E:S:I */
37 [ C(OP_PREFETCH) ] = {
38 [ C(RESULT_ACCESS) ] = 0,
39 [ C(RESULT_MISS) ] = 0,
[all …]
Dcore.c425 [ C(L1D ) ] = {
426 [ C(OP_READ) ] = {
427 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
428 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
430 [ C(OP_WRITE) ] = {
431 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
432 [ C(RESULT_MISS) ] = 0x0,
434 [ C(OP_PREFETCH) ] = {
435 [ C(RESULT_ACCESS) ] = 0x0,
436 [ C(RESULT_MISS) ] = 0x0,
[all …]
Dknc.c26 [ C(L1D) ] = {
27 [ C(OP_READ) ] = {
32 [ C(RESULT_ACCESS) ] = ARCH_PERFMON_EVENTSEL_INT,
34 [ C(RESULT_MISS) ] = 0x0003, /* DATA_READ_MISS */
36 [ C(OP_WRITE) ] = {
37 [ C(RESULT_ACCESS) ] = 0x0001, /* DATA_WRITE */
38 [ C(RESULT_MISS) ] = 0x0004, /* DATA_WRITE_MISS */
40 [ C(OP_PREFETCH) ] = {
41 [ C(RESULT_ACCESS) ] = 0x0011, /* L1_DATA_PF1 */
42 [ C(RESULT_MISS) ] = 0x001c, /* L1_DATA_PF1_MISS */
[all …]
/Linux-v5.4/arch/arm/kernel/
Dperf_event_v7.c179 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
180 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
181 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
182 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
184 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
185 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
187 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
188 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
189 [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
190 [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
[all …]
Dperf_event_v6.c96 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS,
97 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS,
98 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS,
99 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS,
101 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS,
109 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS,
110 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS,
112 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS,
113 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS,
159 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS,
[all …]
/Linux-v5.4/arch/x86/events/amd/
Dcore.c22 [ C(L1D) ] = {
23 [ C(OP_READ) ] = {
24 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
25 [ C(RESULT_MISS) ] = 0x0141, /* Data Cache Misses */
27 [ C(OP_WRITE) ] = {
28 [ C(RESULT_ACCESS) ] = 0,
29 [ C(RESULT_MISS) ] = 0,
31 [ C(OP_PREFETCH) ] = {
32 [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */
33 [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */
[all …]
/Linux-v5.4/lib/
Dsha1.c55 #define SHA_ROUND(t, input, fn, constant, A, B, C, D, E) do { \ argument
60 #define T_0_15(t, A, B, C, D, E) SHA_ROUND(t, SHA_SRC, (((C^D)&B)^D) , 0x5a827999, A, B, C, D, E ) argument
61 #define T_16_19(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, (((C^D)&B)^D) , 0x5a827999, A, B, C, D, E ) argument
62 #define T_20_39(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, (B^C^D) , 0x6ed9eba1, A, B, C, D, E ) argument
63 #define T_40_59(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, ((B&C)+(D&(B^C))) , 0x8f1bbcdc, A, B, C, D,… argument
64 #define T_60_79(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, (B^C^D) , 0xca62c1d6, A, B, C, D, E ) argument
84 __u32 A, B, C, D, E; in sha_transform() local
88 C = digest[2]; in sha_transform()
93 T_0_15( 0, A, B, C, D, E); in sha_transform()
94 T_0_15( 1, E, A, B, C, D); in sha_transform()
[all …]
/Linux-v5.4/tools/testing/selftests/bpf/progs/
Dtest_verif_scale1.c20 #define C do { \ in balancer_ingress() macro
26 #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; in balancer_ingress()
Dtest_verif_scale2.c20 #define C do { \ in balancer_ingress() macro
26 #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; in balancer_ingress()
Dtest_verif_scale3.c20 #define C do { \ in balancer_ingress() macro
26 #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; in balancer_ingress()
/Linux-v5.4/arch/sparc/kernel/
Dperf_event.c147 #define C(x) PERF_COUNT_HW_CACHE_##x macro
221 [C(L1D)] = {
222 [C(OP_READ)] = {
223 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
224 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
226 [C(OP_WRITE)] = {
227 [C(RESULT_ACCESS)] = { 0x0a, PIC_LOWER },
228 [C(RESULT_MISS)] = { 0x0a, PIC_UPPER },
230 [C(OP_PREFETCH)] = {
231 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
[all …]
/Linux-v5.4/arch/nds32/include/asm/
Dpmu.h14 #define C(_x) PERF_COUNT_HW_CACHE_##_x macro
244 [C(L1D)] = {
245 [C(OP_READ)] = {
246 [C(RESULT_ACCESS)] =
248 [C(RESULT_MISS)] =
251 [C(OP_WRITE)] = {
252 [C(RESULT_ACCESS)] =
254 [C(RESULT_MISS)] =
257 [C(OP_PREFETCH)] = {
258 [C(RESULT_ACCESS)] =
[all …]
/Linux-v5.4/arch/mips/kernel/
Dperf_event_mipsxx.c74 #define C(x) PERF_COUNT_HW_CACHE_##x macro
875 [C(L1D)] = {
882 [C(OP_READ)] = {
883 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
884 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
886 [C(OP_WRITE)] = {
887 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
888 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
891 [C(L1I)] = {
892 [C(OP_READ)] = {
[all …]
/Linux-v5.4/arch/riscv/kernel/
Dperf_event.c52 #define C(x) PERF_COUNT_HW_CACHE_##x macro
56 [C(L1D)] = {
57 [C(OP_READ)] = {
58 [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
59 [C(RESULT_MISS)] = RISCV_OP_UNSUPP,
61 [C(OP_WRITE)] = {
62 [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
63 [C(RESULT_MISS)] = RISCV_OP_UNSUPP,
65 [C(OP_PREFETCH)] = {
66 [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
[all …]
/Linux-v5.4/arch/arm64/kernel/
Dperf_event.c57 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
58 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
60 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
61 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
63 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL,
64 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB,
66 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
67 [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB,
69 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
70 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
[all …]
/Linux-v5.4/kernel/trace/
Dtrace_probe.h389 C(FILE_NOT_FOUND, "Failed to find the given file"), \
390 C(NO_REGULAR_FILE, "Not a regular file"), \
391 C(BAD_REFCNT, "Invalid reference counter offset"), \
392 C(REFCNT_OPEN_BRACE, "Reference counter brace is not closed"), \
393 C(BAD_REFCNT_SUFFIX, "Reference counter has wrong suffix"), \
394 C(BAD_UPROBE_OFFS, "Invalid uprobe offset"), \
395 C(MAXACT_NO_KPROBE, "Maxactive is not for kprobe"), \
396 C(BAD_MAXACT, "Invalid maxactive number"), \
397 C(MAXACT_TOO_BIG, "Maxactive is too big"), \
398 C(BAD_PROBE_ADDR, "Invalid probed address or symbol"), \
[all …]
/Linux-v5.4/drivers/scsi/isci/
Drequest.h228 C(REQ_INIT),\
229 C(REQ_CONSTRUCTED),\
230 C(REQ_STARTED),\
231 C(REQ_STP_UDMA_WAIT_TC_COMP),\
232 C(REQ_STP_UDMA_WAIT_D2H),\
233 C(REQ_STP_NON_DATA_WAIT_H2D),\
234 C(REQ_STP_NON_DATA_WAIT_D2H),\
235 C(REQ_STP_PIO_WAIT_H2D),\
236 C(REQ_STP_PIO_WAIT_FRAME),\
237 C(REQ_STP_PIO_DATA_IN),\
[all …]

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