Lines Matching refs:C
74 #define C(x) PERF_COUNT_HW_CACHE_##x macro
875 [C(L1D)] = {
882 [C(OP_READ)] = {
883 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
884 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
886 [C(OP_WRITE)] = {
887 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
888 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
891 [C(L1I)] = {
892 [C(OP_READ)] = {
893 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
894 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
896 [C(OP_WRITE)] = {
897 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
898 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
900 [C(OP_PREFETCH)] = {
901 [C(RESULT_ACCESS)] = { 0x14, CNTR_EVEN, T },
908 [C(LL)] = {
909 [C(OP_READ)] = {
910 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
911 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },
913 [C(OP_WRITE)] = {
914 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
915 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },
918 [C(DTLB)] = {
919 [C(OP_READ)] = {
920 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
921 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
923 [C(OP_WRITE)] = {
924 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
925 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
928 [C(ITLB)] = {
929 [C(OP_READ)] = {
930 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
931 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
933 [C(OP_WRITE)] = {
934 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
935 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
938 [C(BPU)] = {
940 [C(OP_READ)] = {
941 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
942 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
944 [C(OP_WRITE)] = {
945 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
946 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
956 [C(L1D)] = {
963 [C(OP_READ)] = {
964 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
965 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
967 [C(OP_WRITE)] = {
968 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
969 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
972 [C(L1I)] = {
973 [C(OP_READ)] = {
974 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
975 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
977 [C(OP_WRITE)] = {
978 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
979 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
981 [C(OP_PREFETCH)] = {
982 [C(RESULT_ACCESS)] = { 0x34, CNTR_EVEN, T },
989 [C(LL)] = {
990 [C(OP_READ)] = {
991 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
992 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P },
994 [C(OP_WRITE)] = {
995 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
996 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P },
1004 [C(ITLB)] = {
1005 [C(OP_READ)] = {
1006 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
1007 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
1009 [C(OP_WRITE)] = {
1010 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
1011 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
1014 [C(BPU)] = {
1016 [C(OP_READ)] = {
1017 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
1018 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
1020 [C(OP_WRITE)] = {
1021 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
1022 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
1031 [C(L1D)] = {
1032 [C(OP_READ)] = {
1033 [C(RESULT_ACCESS)] = { 0x46, CNTR_EVEN | CNTR_ODD },
1034 [C(RESULT_MISS)] = { 0x49, CNTR_EVEN | CNTR_ODD },
1036 [C(OP_WRITE)] = {
1037 [C(RESULT_ACCESS)] = { 0x47, CNTR_EVEN | CNTR_ODD },
1038 [C(RESULT_MISS)] = { 0x4a, CNTR_EVEN | CNTR_ODD },
1041 [C(L1I)] = {
1042 [C(OP_READ)] = {
1043 [C(RESULT_ACCESS)] = { 0x84, CNTR_EVEN | CNTR_ODD },
1044 [C(RESULT_MISS)] = { 0x85, CNTR_EVEN | CNTR_ODD },
1047 [C(DTLB)] = {
1049 [C(OP_READ)] = {
1050 [C(RESULT_ACCESS)] = { 0x40, CNTR_EVEN | CNTR_ODD },
1051 [C(RESULT_MISS)] = { 0x41, CNTR_EVEN | CNTR_ODD },
1053 [C(OP_WRITE)] = {
1054 [C(RESULT_ACCESS)] = { 0x40, CNTR_EVEN | CNTR_ODD },
1055 [C(RESULT_MISS)] = { 0x41, CNTR_EVEN | CNTR_ODD },
1058 [C(BPU)] = {
1060 [C(OP_READ)] = {
1061 [C(RESULT_ACCESS)] = { 0x15, CNTR_EVEN | CNTR_ODD },
1062 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN | CNTR_ODD },
1071 [C(L1D)] = {
1078 [C(OP_READ)] = {
1079 [C(RESULT_MISS)] = { 0x04, CNTR_ODD },
1081 [C(OP_WRITE)] = {
1082 [C(RESULT_MISS)] = { 0x04, CNTR_ODD },
1085 [C(L1I)] = {
1086 [C(OP_READ)] = {
1087 [C(RESULT_MISS)] = { 0x04, CNTR_EVEN },
1089 [C(OP_WRITE)] = {
1090 [C(RESULT_MISS)] = { 0x04, CNTR_EVEN },
1093 [C(DTLB)] = {
1094 [C(OP_READ)] = {
1095 [C(RESULT_MISS)] = { 0x09, CNTR_ODD },
1097 [C(OP_WRITE)] = {
1098 [C(RESULT_MISS)] = { 0x09, CNTR_ODD },
1101 [C(ITLB)] = {
1102 [C(OP_READ)] = {
1103 [C(RESULT_MISS)] = { 0x0c, CNTR_ODD },
1105 [C(OP_WRITE)] = {
1106 [C(RESULT_MISS)] = { 0x0c, CNTR_ODD },
1109 [C(BPU)] = {
1111 [C(OP_READ)] = {
1112 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN },
1113 [C(RESULT_MISS)] = { 0x02, CNTR_ODD },
1115 [C(OP_WRITE)] = {
1116 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN },
1117 [C(RESULT_MISS)] = { 0x02, CNTR_ODD },
1127 [C(L1D)] = {
1134 [C(OP_READ)] = {
1135 [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T },
1136 [C(RESULT_MISS)] = { 12, CNTR_ODD, T },
1138 [C(OP_WRITE)] = {
1139 [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T },
1140 [C(RESULT_MISS)] = { 12, CNTR_ODD, T },
1143 [C(L1I)] = {
1144 [C(OP_READ)] = {
1145 [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T },
1146 [C(RESULT_MISS)] = { 10, CNTR_ODD, T },
1148 [C(OP_WRITE)] = {
1149 [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T },
1150 [C(RESULT_MISS)] = { 10, CNTR_ODD, T },
1152 [C(OP_PREFETCH)] = {
1153 [C(RESULT_ACCESS)] = { 23, CNTR_EVEN, T },
1160 [C(LL)] = {
1161 [C(OP_READ)] = {
1162 [C(RESULT_ACCESS)] = { 28, CNTR_EVEN, P },
1163 [C(RESULT_MISS)] = { 28, CNTR_ODD, P },
1165 [C(OP_WRITE)] = {
1166 [C(RESULT_ACCESS)] = { 28, CNTR_EVEN, P },
1167 [C(RESULT_MISS)] = { 28, CNTR_ODD, P },
1170 [C(BPU)] = {
1172 [C(OP_READ)] = {
1173 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1175 [C(OP_WRITE)] = {
1176 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1186 [C(L1D)] = {
1187 [C(OP_READ)] = {
1188 [C(RESULT_ACCESS)] = { 0x2b, CNTR_ALL },
1189 [C(RESULT_MISS)] = { 0x2e, CNTR_ALL },
1191 [C(OP_WRITE)] = {
1192 [C(RESULT_ACCESS)] = { 0x30, CNTR_ALL },
1195 [C(L1I)] = {
1196 [C(OP_READ)] = {
1197 [C(RESULT_ACCESS)] = { 0x18, CNTR_ALL },
1199 [C(OP_PREFETCH)] = {
1200 [C(RESULT_ACCESS)] = { 0x19, CNTR_ALL },
1203 [C(DTLB)] = {
1208 [C(OP_READ)] = {
1209 [C(RESULT_MISS)] = { 0x35, CNTR_ALL },
1211 [C(OP_WRITE)] = {
1212 [C(RESULT_MISS)] = { 0x35, CNTR_ALL },
1215 [C(ITLB)] = {
1216 [C(OP_READ)] = {
1217 [C(RESULT_MISS)] = { 0x37, CNTR_ALL },
1226 [C(L1D)] = {
1227 [C(OP_READ)] = {
1228 [C(RESULT_ACCESS)] = { 0x31, CNTR_ALL }, /* PAPI_L1_DCR */
1229 [C(RESULT_MISS)] = { 0x30, CNTR_ALL }, /* PAPI_L1_LDM */
1231 [C(OP_WRITE)] = {
1232 [C(RESULT_ACCESS)] = { 0x2f, CNTR_ALL }, /* PAPI_L1_DCW */
1233 [C(RESULT_MISS)] = { 0x2e, CNTR_ALL }, /* PAPI_L1_STM */
1236 [C(L1I)] = {
1237 [C(OP_READ)] = {
1238 [C(RESULT_ACCESS)] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */
1239 [C(RESULT_MISS)] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */
1242 [C(LL)] = {
1243 [C(OP_READ)] = {
1244 [C(RESULT_ACCESS)] = { 0x35, CNTR_ALL }, /* PAPI_L2_DCR */
1245 [C(RESULT_MISS)] = { 0x37, CNTR_ALL }, /* PAPI_L2_LDM */
1247 [C(OP_WRITE)] = {
1248 [C(RESULT_ACCESS)] = { 0x34, CNTR_ALL }, /* PAPI_L2_DCA */
1249 [C(RESULT_MISS)] = { 0x36, CNTR_ALL }, /* PAPI_L2_DCM */
1252 [C(DTLB)] = {
1257 [C(OP_READ)] = {
1258 [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
1260 [C(OP_WRITE)] = {
1261 [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
1264 [C(ITLB)] = {
1265 [C(OP_READ)] = {
1266 [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
1268 [C(OP_WRITE)] = {
1269 [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
1272 [C(BPU)] = {
1273 [C(OP_READ)] = {
1274 [C(RESULT_MISS)] = { 0x25, CNTR_ALL },