Lines Matching refs:C
22 [ C(L1D) ] = {
23 [ C(OP_READ) ] = {
24 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
25 [ C(RESULT_MISS) ] = 0x0141, /* Data Cache Misses */
27 [ C(OP_WRITE) ] = {
28 [ C(RESULT_ACCESS) ] = 0,
29 [ C(RESULT_MISS) ] = 0,
31 [ C(OP_PREFETCH) ] = {
32 [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */
33 [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */
36 [ C(L1I ) ] = {
37 [ C(OP_READ) ] = {
38 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches */
39 [ C(RESULT_MISS) ] = 0x0081, /* Instruction cache misses */
41 [ C(OP_WRITE) ] = {
42 [ C(RESULT_ACCESS) ] = -1,
43 [ C(RESULT_MISS) ] = -1,
45 [ C(OP_PREFETCH) ] = {
46 [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */
47 [ C(RESULT_MISS) ] = 0,
50 [ C(LL ) ] = {
51 [ C(OP_READ) ] = {
52 [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */
53 [ C(RESULT_MISS) ] = 0x037E, /* L2 Cache Misses : IC+DC */
55 [ C(OP_WRITE) ] = {
56 [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback */
57 [ C(RESULT_MISS) ] = 0,
59 [ C(OP_PREFETCH) ] = {
60 [ C(RESULT_ACCESS) ] = 0,
61 [ C(RESULT_MISS) ] = 0,
64 [ C(DTLB) ] = {
65 [ C(OP_READ) ] = {
66 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
67 [ C(RESULT_MISS) ] = 0x0746, /* L1_DTLB_AND_L2_DLTB_MISS.ALL */
69 [ C(OP_WRITE) ] = {
70 [ C(RESULT_ACCESS) ] = 0,
71 [ C(RESULT_MISS) ] = 0,
73 [ C(OP_PREFETCH) ] = {
74 [ C(RESULT_ACCESS) ] = 0,
75 [ C(RESULT_MISS) ] = 0,
78 [ C(ITLB) ] = {
79 [ C(OP_READ) ] = {
80 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes */
81 [ C(RESULT_MISS) ] = 0x0385, /* L1_ITLB_AND_L2_ITLB_MISS.ALL */
83 [ C(OP_WRITE) ] = {
84 [ C(RESULT_ACCESS) ] = -1,
85 [ C(RESULT_MISS) ] = -1,
87 [ C(OP_PREFETCH) ] = {
88 [ C(RESULT_ACCESS) ] = -1,
89 [ C(RESULT_MISS) ] = -1,
92 [ C(BPU ) ] = {
93 [ C(OP_READ) ] = {
94 [ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr. */
95 [ C(RESULT_MISS) ] = 0x00c3, /* Retired Mispredicted BI */
97 [ C(OP_WRITE) ] = {
98 [ C(RESULT_ACCESS) ] = -1,
99 [ C(RESULT_MISS) ] = -1,
101 [ C(OP_PREFETCH) ] = {
102 [ C(RESULT_ACCESS) ] = -1,
103 [ C(RESULT_MISS) ] = -1,
106 [ C(NODE) ] = {
107 [ C(OP_READ) ] = {
108 [ C(RESULT_ACCESS) ] = 0xb8e9, /* CPU Request to Memory, l+r */
109 [ C(RESULT_MISS) ] = 0x98e9, /* CPU Request to Memory, r */
111 [ C(OP_WRITE) ] = {
112 [ C(RESULT_ACCESS) ] = -1,
113 [ C(RESULT_MISS) ] = -1,
115 [ C(OP_PREFETCH) ] = {
116 [ C(RESULT_ACCESS) ] = -1,
117 [ C(RESULT_MISS) ] = -1,
126 [C(L1D)] = {
127 [C(OP_READ)] = {
128 [C(RESULT_ACCESS)] = 0x0040, /* Data Cache Accesses */
129 [C(RESULT_MISS)] = 0xc860, /* L2$ access from DC Miss */
131 [C(OP_WRITE)] = {
132 [C(RESULT_ACCESS)] = 0,
133 [C(RESULT_MISS)] = 0,
135 [C(OP_PREFETCH)] = {
136 [C(RESULT_ACCESS)] = 0xff5a, /* h/w prefetch DC Fills */
137 [C(RESULT_MISS)] = 0,
140 [C(L1I)] = {
141 [C(OP_READ)] = {
142 [C(RESULT_ACCESS)] = 0x0080, /* Instruction cache fetches */
143 [C(RESULT_MISS)] = 0x0081, /* Instruction cache misses */
145 [C(OP_WRITE)] = {
146 [C(RESULT_ACCESS)] = -1,
147 [C(RESULT_MISS)] = -1,
149 [C(OP_PREFETCH)] = {
150 [C(RESULT_ACCESS)] = 0,
151 [C(RESULT_MISS)] = 0,
154 [C(LL)] = {
155 [C(OP_READ)] = {
156 [C(RESULT_ACCESS)] = 0,
157 [C(RESULT_MISS)] = 0,
159 [C(OP_WRITE)] = {
160 [C(RESULT_ACCESS)] = 0,
161 [C(RESULT_MISS)] = 0,
163 [C(OP_PREFETCH)] = {
164 [C(RESULT_ACCESS)] = 0,
165 [C(RESULT_MISS)] = 0,
168 [C(DTLB)] = {
169 [C(OP_READ)] = {
170 [C(RESULT_ACCESS)] = 0xff45, /* All L2 DTLB accesses */
171 [C(RESULT_MISS)] = 0xf045, /* L2 DTLB misses (PT walks) */
173 [C(OP_WRITE)] = {
174 [C(RESULT_ACCESS)] = 0,
175 [C(RESULT_MISS)] = 0,
177 [C(OP_PREFETCH)] = {
178 [C(RESULT_ACCESS)] = 0,
179 [C(RESULT_MISS)] = 0,
182 [C(ITLB)] = {
183 [C(OP_READ)] = {
184 [C(RESULT_ACCESS)] = 0x0084, /* L1 ITLB misses, L2 ITLB hits */
185 [C(RESULT_MISS)] = 0xff85, /* L1 ITLB misses, L2 misses */
187 [C(OP_WRITE)] = {
188 [C(RESULT_ACCESS)] = -1,
189 [C(RESULT_MISS)] = -1,
191 [C(OP_PREFETCH)] = {
192 [C(RESULT_ACCESS)] = -1,
193 [C(RESULT_MISS)] = -1,
196 [C(BPU)] = {
197 [C(OP_READ)] = {
198 [C(RESULT_ACCESS)] = 0x00c2, /* Retired Branch Instr. */
199 [C(RESULT_MISS)] = 0x00c3, /* Retired Mispredicted BI */
201 [C(OP_WRITE)] = {
202 [C(RESULT_ACCESS)] = -1,
203 [C(RESULT_MISS)] = -1,
205 [C(OP_PREFETCH)] = {
206 [C(RESULT_ACCESS)] = -1,
207 [C(RESULT_MISS)] = -1,
210 [C(NODE)] = {
211 [C(OP_READ)] = {
212 [C(RESULT_ACCESS)] = 0,
213 [C(RESULT_MISS)] = 0,
215 [C(OP_WRITE)] = {
216 [C(RESULT_ACCESS)] = -1,
217 [C(RESULT_MISS)] = -1,
219 [C(OP_PREFETCH)] = {
220 [C(RESULT_ACCESS)] = -1,
221 [C(RESULT_MISS)] = -1,