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Searched refs:pipe_config (Results 1 – 25 of 29) sorted by relevance

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/Linux-v4.19/drivers/gpu/drm/i915/
Dintel_hdmi.c190 const struct intel_crtc_state *pipe_config) in g4x_infoframe_enabled() argument
247 const struct intel_crtc_state *pipe_config) in ibx_infoframe_enabled() argument
251 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; in ibx_infoframe_enabled()
310 const struct intel_crtc_state *pipe_config) in cpt_infoframe_enabled() argument
313 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; in cpt_infoframe_enabled()
365 const struct intel_crtc_state *pipe_config) in vlv_infoframe_enabled() argument
369 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; in vlv_infoframe_enabled()
419 const struct intel_crtc_state *pipe_config) in hsw_infoframe_enabled() argument
422 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); in hsw_infoframe_enabled()
1194 struct intel_crtc_state *pipe_config) in intel_hdmi_get_config() argument
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Dintel_dp_mst.c34 struct intel_crtc_state *pipe_config, in intel_dp_mst_compute_config() argument
43 struct drm_atomic_state *state = pipe_config->base.state; in intel_dp_mst_compute_config()
46 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_dp_mst_compute_config()
54 pipe_config->has_pch_encoder = false; in intel_dp_mst_compute_config()
67 pipe_config->lane_count = lane_count; in intel_dp_mst_compute_config()
69 pipe_config->pipe_bpp = bpp; in intel_dp_mst_compute_config()
71 pipe_config->port_clock = intel_dp_max_link_rate(intel_dp); in intel_dp_mst_compute_config()
74 pipe_config->has_audio = true; in intel_dp_mst_compute_config()
77 pipe_config->pbn = mst_pbn; in intel_dp_mst_compute_config()
88 pipe_config->port_clock, in intel_dp_mst_compute_config()
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Dintel_display.c136 struct intel_crtc_state *pipe_config);
138 struct intel_crtc_state *pipe_config);
153 const struct intel_crtc_state *pipe_config);
155 const struct intel_crtc_state *pipe_config);
234 const struct intel_crtc_state *pipe_config) in intel_fdi_link_freq() argument
237 return pipe_config->port_clock; /* SPLL */ in intel_fdi_link_freq()
1389 const struct intel_crtc_state *pipe_config) in _vlv_enable_pll() argument
1394 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _vlv_enable_pll()
1407 const struct intel_crtc_state *pipe_config) in vlv_enable_pll() argument
1417 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) in vlv_enable_pll()
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Dintel_lvds.c121 struct intel_crtc_state *pipe_config) in intel_lvds_get_config() argument
127 pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS); in intel_lvds_get_config()
139 pipe_config->base.adjusted_mode.flags |= flags; in intel_lvds_get_config()
142 pipe_config->gmch_pfit.lvds_border_bits = in intel_lvds_get_config()
149 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; in intel_lvds_get_config()
152 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_lvds_get_config()
233 const struct intel_crtc_state *pipe_config, in intel_pre_enable_lvds() argument
238 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); in intel_pre_enable_lvds()
239 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_pre_enable_lvds()
246 pipe_config->shared_dpll); in intel_pre_enable_lvds()
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Dintel_ddi.c1430 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) in ddi_dotclock_get() argument
1434 if (pipe_config->has_pch_encoder) in ddi_dotclock_get()
1435 dotclock = intel_dotclock_calculate(pipe_config->port_clock, in ddi_dotclock_get()
1436 &pipe_config->fdi_m_n); in ddi_dotclock_get()
1437 else if (intel_crtc_has_dp_encoder(pipe_config)) in ddi_dotclock_get()
1438 dotclock = intel_dotclock_calculate(pipe_config->port_clock, in ddi_dotclock_get()
1439 &pipe_config->dp_m_n); in ddi_dotclock_get()
1440 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36) in ddi_dotclock_get()
1441 dotclock = pipe_config->port_clock * 2 / 3; in ddi_dotclock_get()
1443 dotclock = pipe_config->port_clock; in ddi_dotclock_get()
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Dintel_crt.c122 struct intel_crtc_state *pipe_config) in intel_crt_get_config() argument
124 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); in intel_crt_get_config()
126 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); in intel_crt_get_config()
128 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_crt_get_config()
132 struct intel_crtc_state *pipe_config) in hsw_crt_get_config() argument
136 intel_ddi_get_config(encoder, pipe_config); in hsw_crt_get_config()
138 pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | in hsw_crt_get_config()
142 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); in hsw_crt_get_config()
144 pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv); in hsw_crt_get_config()
348 struct intel_crtc_state *pipe_config, in intel_crt_compute_config() argument
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Dintel_dvo.c152 struct intel_crtc_state *pipe_config) in intel_dvo_get_config() argument
158 pipe_config->output_types |= BIT(INTEL_OUTPUT_DVO); in intel_dvo_get_config()
170 pipe_config->base.adjusted_mode.flags |= flags; in intel_dvo_get_config()
172 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_dvo_get_config()
190 const struct intel_crtc_state *pipe_config, in intel_enable_dvo() argument
199 &pipe_config->base.mode, in intel_enable_dvo()
200 &pipe_config->base.adjusted_mode); in intel_enable_dvo()
239 struct intel_crtc_state *pipe_config, in intel_dvo_compute_config() argument
245 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_dvo_compute_config()
263 const struct intel_crtc_state *pipe_config, in intel_dvo_pre_enable() argument
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Dvlv_dsi.c304 struct intel_crtc_state *pipe_config, in intel_dsi_compute_config() argument
311 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); in intel_dsi_compute_config()
313 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_dsi_compute_config()
322 intel_gmch_panel_fitting(crtc, pipe_config, in intel_dsi_compute_config()
325 intel_pch_panel_fitting(crtc, pipe_config, in intel_dsi_compute_config()
342 pipe_config->cpu_transcoder = TRANSCODER_DSI_C; in intel_dsi_compute_config()
344 pipe_config->cpu_transcoder = TRANSCODER_DSI_A; in intel_dsi_compute_config()
346 ret = bxt_dsi_pll_compute(encoder, pipe_config); in intel_dsi_compute_config()
350 ret = vlv_dsi_pll_compute(encoder, pipe_config); in intel_dsi_compute_config()
355 pipe_config->clock_set = true; in intel_dsi_compute_config()
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Dintel_dp.c1552 struct intel_crtc_state *pipe_config) in intel_dp_set_clock() argument
1574 if (pipe_config->port_clock == divisor[i].clock) { in intel_dp_set_clock()
1575 pipe_config->dpll = divisor[i].dpll; in intel_dp_set_clock()
1576 pipe_config->clock_set = true; in intel_dp_set_clock()
1663 struct intel_crtc_state *pipe_config) in intel_dp_compute_bpp() argument
1669 bpp = pipe_config->pipe_bpp; in intel_dp_compute_bpp()
1691 struct intel_crtc_state *pipe_config, in intel_dp_adjust_compliance_config() argument
1699 pipe_config->dither_force_disable = bpp == 6 * 3; in intel_dp_adjust_compliance_config()
1727 struct intel_crtc_state *pipe_config, in intel_dp_compute_link_config_wide() argument
1730 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_dp_compute_link_config_wide()
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Dintel_panel.c105 struct intel_crtc_state *pipe_config, in intel_pch_panel_fitting() argument
108 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_pch_panel_fitting()
112 if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w && in intel_pch_panel_fitting()
113 adjusted_mode->crtc_vdisplay == pipe_config->pipe_src_h && in intel_pch_panel_fitting()
114 !pipe_config->ycbcr420) in intel_pch_panel_fitting()
119 width = pipe_config->pipe_src_w; in intel_pch_panel_fitting()
120 height = pipe_config->pipe_src_h; in intel_pch_panel_fitting()
129 * pipe_config->pipe_src_h; in intel_pch_panel_fitting()
130 u32 scaled_height = pipe_config->pipe_src_w in intel_pch_panel_fitting()
133 width = scaled_height / pipe_config->pipe_src_h; in intel_pch_panel_fitting()
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Dintel_pipe_crc.c337 struct intel_crtc_state *pipe_config; in hsw_pipe_A_crc_wa() local
353 pipe_config = intel_atomic_get_crtc_state(state, crtc); in hsw_pipe_A_crc_wa()
354 if (IS_ERR(pipe_config)) { in hsw_pipe_A_crc_wa()
355 ret = PTR_ERR(pipe_config); in hsw_pipe_A_crc_wa()
366 pipe_config->ips_force_disable = enable; in hsw_pipe_A_crc_wa()
370 pipe_config->pch_pfit.force_thru = enable; in hsw_pipe_A_crc_wa()
371 if (pipe_config->cpu_transcoder == TRANSCODER_EDP && in hsw_pipe_A_crc_wa()
372 pipe_config->pch_pfit.enabled != enable) in hsw_pipe_A_crc_wa()
373 pipe_config->base.connectors_changed = true; in hsw_pipe_A_crc_wa()
Dintel_sdvo.c998 const struct intel_crtc_state *pipe_config) in intel_sdvo_set_avi_infoframe() argument
1006 &pipe_config->base.adjusted_mode, in intel_sdvo_set_avi_infoframe()
1014 if (pipe_config->limited_color_range) in intel_sdvo_set_avi_infoframe()
1095 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) in i9xx_adjust_sdvo_tv_clock() argument
1097 unsigned dotclock = pipe_config->port_clock; in i9xx_adjust_sdvo_tv_clock()
1098 struct dpll *clock = &pipe_config->dpll; in i9xx_adjust_sdvo_tv_clock()
1120 pipe_config->clock_set = true; in i9xx_adjust_sdvo_tv_clock()
1124 struct intel_crtc_state *pipe_config, in intel_sdvo_compute_config() argument
1130 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_sdvo_compute_config()
1131 struct drm_display_mode *mode = &pipe_config->base.mode; in intel_sdvo_compute_config()
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Dintel_tv.c811 const struct intel_crtc_state *pipe_config, in intel_enable_tv() argument
819 to_intel_crtc(pipe_config->base.crtc)->pipe); in intel_enable_tv()
866 struct intel_crtc_state *pipe_config) in intel_tv_get_config() argument
868 pipe_config->output_types |= BIT(INTEL_OUTPUT_TVOUT); in intel_tv_get_config()
870 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_tv_get_config()
875 struct intel_crtc_state *pipe_config, in intel_tv_compute_config() argument
880 &pipe_config->base.adjusted_mode; in intel_tv_compute_config()
890 pipe_config->pipe_bpp = 8*3; in intel_tv_compute_config()
983 const struct intel_crtc_state *pipe_config, in intel_tv_pre_enable() argument
987 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); in intel_tv_pre_enable()
Dintel_drv.h255 struct intel_crtc_state *pipe_config);
1181 const struct intel_crtc_state *pipe_config);
1418 struct intel_crtc_state *pipe_config);
1623 struct intel_crtc_state *pipe_config);
1636 struct intel_crtc_state *pipe_config);
1691 struct intel_crtc_state *pipe_config,
1838 struct intel_crtc_state *pipe_config,
1884 struct intel_crtc_state *pipe_config,
1887 struct intel_crtc_state *pipe_config,
Dicl_dsi.c116 const struct intel_crtc_state *pipe_config, in gen11_dsi_pre_enable() argument
Dintel_overlay.c929 const struct intel_crtc_state *pipe_config = in check_overlay_dst() local
932 if (rec->dst_x < pipe_config->pipe_src_w && in check_overlay_dst()
933 rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w && in check_overlay_dst()
934 rec->dst_y < pipe_config->pipe_src_h && in check_overlay_dst()
935 rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h) in check_overlay_dst()
Di915_debugfs.c3155 struct intel_crtc_state *pipe_config; in intel_scaler_info() local
3159 pipe_config = to_intel_crtc_state(intel_crtc->base.state); in intel_scaler_info()
3165 pipe_config->scaler_state.scaler_users, in intel_scaler_info()
3166 pipe_config->scaler_state.scaler_id); in intel_scaler_info()
3170 &pipe_config->scaler_state.scalers[i]; in intel_scaler_info()
3193 struct intel_crtc_state *pipe_config; in i915_display_info() local
3196 pipe_config = to_intel_crtc_state(crtc->base.state); in i915_display_info()
3200 yesno(pipe_config->base.active), in i915_display_info()
3201 pipe_config->pipe_src_w, pipe_config->pipe_src_h, in i915_display_info()
3202 yesno(pipe_config->dither), pipe_config->pipe_bpp); in i915_display_info()
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/Linux-v4.19/drivers/usb/renesas_usbhs/
Dpipe.c462 struct renesas_usbhs_driver_pipe_config *pipe_config = in usbhsp_setup_pipebuff() local
474 buff_size = pipe_config->bufsize; in usbhsp_setup_pipebuff()
475 bufnmb = pipe_config->bufnum; in usbhsp_setup_pipebuff()
492 struct renesas_usbhs_driver_pipe_config *pipe_config = in usbhs_pipe_config_update() local
494 u16 dblb = pipe_config->double_buf ? DBLB : 0; in usbhs_pipe_config_update()
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/core/
Ddc_debug.c162 plane_state->tiling_info.gfx8.pipe_config, in pre_surface_trace()
251 update->plane_info->tiling_info.gfx8.pipe_config, in update_surface_trace()
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/
Ddc_hw_types.h347 unsigned int pipe_config; member
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/dce/
Ddce_mem_input.c380 GRPH_PIPE_CONFIG, info->gfx8.pipe_config, in program_tiling()
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_mem_input_v.c189 set_reg_field_value(value, info->gfx8.pipe_config, in program_tiling()
/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Ddce_v8_0.c1763 u32 pipe_config; in dce_v8_0_crtc_do_set_base() local
1801 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v8_0_crtc_do_set_base()
1893 fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT); in dce_v8_0_crtc_do_set_base()
Ddce_v6_0.c1787 uint32_t fb_format, fb_pitch_pixels, pipe_config; in dce_v6_0_crtc_do_set_base() local
1915 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v6_0_crtc_do_set_base()
1916 fb_format |= GRPH_PIPE_CONFIG(pipe_config); in dce_v6_0_crtc_do_set_base()
/Linux-v4.19/drivers/gpu/drm/radeon/
Datombios_crtc.c1344 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f; in dce4_crtc_do_set_base() local
1346 fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config); in dce4_crtc_do_set_base()

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