Lines Matching refs:pipe_config
1430 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) in ddi_dotclock_get() argument
1434 if (pipe_config->has_pch_encoder) in ddi_dotclock_get()
1435 dotclock = intel_dotclock_calculate(pipe_config->port_clock, in ddi_dotclock_get()
1436 &pipe_config->fdi_m_n); in ddi_dotclock_get()
1437 else if (intel_crtc_has_dp_encoder(pipe_config)) in ddi_dotclock_get()
1438 dotclock = intel_dotclock_calculate(pipe_config->port_clock, in ddi_dotclock_get()
1439 &pipe_config->dp_m_n); in ddi_dotclock_get()
1440 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36) in ddi_dotclock_get()
1441 dotclock = pipe_config->port_clock * 2 / 3; in ddi_dotclock_get()
1443 dotclock = pipe_config->port_clock; in ddi_dotclock_get()
1445 if (pipe_config->ycbcr420) in ddi_dotclock_get()
1448 if (pipe_config->pixel_multiplier) in ddi_dotclock_get()
1449 dotclock /= pipe_config->pixel_multiplier; in ddi_dotclock_get()
1451 pipe_config->base.adjusted_mode.crtc_clock = dotclock; in ddi_dotclock_get()
1455 struct intel_crtc_state *pipe_config) in icl_ddi_clock_get() argument
1462 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll); in icl_ddi_clock_get()
1464 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) in icl_ddi_clock_get()
1474 pipe_config->port_clock = link_clock; in icl_ddi_clock_get()
1475 ddi_dotclock_get(pipe_config); in icl_ddi_clock_get()
1479 struct intel_crtc_state *pipe_config) in cnl_ddi_clock_get() argument
1486 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll); in cnl_ddi_clock_get()
1527 pipe_config->port_clock = link_clock; in cnl_ddi_clock_get()
1529 ddi_dotclock_get(pipe_config); in cnl_ddi_clock_get()
1533 struct intel_crtc_state *pipe_config) in skl_ddi_clock_get() argument
1540 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll); in skl_ddi_clock_get()
1576 pipe_config->port_clock = link_clock; in skl_ddi_clock_get()
1578 ddi_dotclock_get(pipe_config); in skl_ddi_clock_get()
1582 struct intel_crtc_state *pipe_config) in hsw_ddi_clock_get() argument
1588 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll); in hsw_ddi_clock_get()
1623 pipe_config->port_clock = link_clock * 2; in hsw_ddi_clock_get()
1625 ddi_dotclock_get(pipe_config); in hsw_ddi_clock_get()
1651 struct intel_crtc_state *pipe_config) in bxt_ddi_clock_get() argument
1653 pipe_config->port_clock = bxt_calc_pll_link(pipe_config); in bxt_ddi_clock_get()
1655 ddi_dotclock_get(pipe_config); in bxt_ddi_clock_get()
1659 struct intel_crtc_state *pipe_config) in intel_ddi_clock_get() argument
1664 hsw_ddi_clock_get(encoder, pipe_config); in intel_ddi_clock_get()
1666 skl_ddi_clock_get(encoder, pipe_config); in intel_ddi_clock_get()
1668 bxt_ddi_clock_get(encoder, pipe_config); in intel_ddi_clock_get()
1670 cnl_ddi_clock_get(encoder, pipe_config); in intel_ddi_clock_get()
1672 icl_ddi_clock_get(encoder, pipe_config); in intel_ddi_clock_get()
3065 const struct intel_crtc_state *pipe_config, in bxt_ddi_pre_pll_enable() argument
3068 uint8_t mask = pipe_config->lane_lat_optim_mask; in bxt_ddi_pre_pll_enable()
3142 struct intel_crtc_state *pipe_config) in intel_ddi_get_config() argument
3145 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); in intel_ddi_get_config()
3146 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; in intel_ddi_get_config()
3164 pipe_config->base.adjusted_mode.flags |= flags; in intel_ddi_get_config()
3168 pipe_config->pipe_bpp = 18; in intel_ddi_get_config()
3171 pipe_config->pipe_bpp = 24; in intel_ddi_get_config()
3174 pipe_config->pipe_bpp = 30; in intel_ddi_get_config()
3177 pipe_config->pipe_bpp = 36; in intel_ddi_get_config()
3185 pipe_config->has_hdmi_sink = true; in intel_ddi_get_config()
3188 if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config)) in intel_ddi_get_config()
3189 pipe_config->has_infoframe = true; in intel_ddi_get_config()
3193 pipe_config->hdmi_scrambling = true; in intel_ddi_get_config()
3195 pipe_config->hdmi_high_tmds_clock_ratio = true; in intel_ddi_get_config()
3198 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); in intel_ddi_get_config()
3199 pipe_config->lane_count = 4; in intel_ddi_get_config()
3202 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); in intel_ddi_get_config()
3206 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); in intel_ddi_get_config()
3208 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); in intel_ddi_get_config()
3209 pipe_config->lane_count = in intel_ddi_get_config()
3211 intel_dp_get_m_n(intel_crtc, pipe_config); in intel_ddi_get_config()
3214 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); in intel_ddi_get_config()
3215 pipe_config->lane_count = in intel_ddi_get_config()
3217 intel_dp_get_m_n(intel_crtc, pipe_config); in intel_ddi_get_config()
3223 pipe_config->has_audio = in intel_ddi_get_config()
3227 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { in intel_ddi_get_config()
3242 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); in intel_ddi_get_config()
3243 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; in intel_ddi_get_config()
3246 intel_ddi_clock_get(encoder, pipe_config); in intel_ddi_get_config()
3249 pipe_config->lane_lat_optim_mask = in intel_ddi_get_config()
3252 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); in intel_ddi_get_config()
3274 struct intel_crtc_state *pipe_config, in intel_ddi_compute_config() argument
3282 pipe_config->cpu_transcoder = TRANSCODER_EDP; in intel_ddi_compute_config()
3284 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) in intel_ddi_compute_config()
3285 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); in intel_ddi_compute_config()
3287 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); in intel_ddi_compute_config()
3290 pipe_config->lane_lat_optim_mask = in intel_ddi_compute_config()
3291 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); in intel_ddi_compute_config()
3293 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); in intel_ddi_compute_config()