Lines Matching refs:pipe_config
136 struct intel_crtc_state *pipe_config);
138 struct intel_crtc_state *pipe_config);
153 const struct intel_crtc_state *pipe_config);
155 const struct intel_crtc_state *pipe_config);
234 const struct intel_crtc_state *pipe_config) in intel_fdi_link_freq() argument
237 return pipe_config->port_clock; /* SPLL */ in intel_fdi_link_freq()
1389 const struct intel_crtc_state *pipe_config) in _vlv_enable_pll() argument
1394 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _vlv_enable_pll()
1407 const struct intel_crtc_state *pipe_config) in vlv_enable_pll() argument
1417 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) in vlv_enable_pll()
1418 _vlv_enable_pll(crtc, pipe_config); in vlv_enable_pll()
1420 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); in vlv_enable_pll()
1426 const struct intel_crtc_state *pipe_config) in _chv_enable_pll() argument
1448 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _chv_enable_pll()
1458 const struct intel_crtc_state *pipe_config) in chv_enable_pll() argument
1468 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) in chv_enable_pll()
1469 _chv_enable_pll(crtc, pipe_config); in chv_enable_pll()
1479 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); in chv_enable_pll()
1481 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; in chv_enable_pll()
1489 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); in chv_enable_pll()
5236 struct intel_crtc_state *pipe_config = in intel_post_plane_update() local
5243 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits); in intel_post_plane_update()
5245 if (pipe_config->update_wm_post && pipe_config->base.active) in intel_post_plane_update()
5248 if (hsw_post_update_enable_ips(old_crtc_state, pipe_config)) in intel_post_plane_update()
5249 hsw_enable_ips(pipe_config); in intel_post_plane_update()
5258 (needs_modeset(&pipe_config->base) || in intel_post_plane_update()
5260 intel_post_enable_primary(&crtc->base, pipe_config); in intel_post_plane_update()
5265 !needs_nv12_wa(dev_priv, pipe_config)) { in intel_post_plane_update()
5272 struct intel_crtc_state *pipe_config) in intel_pre_plane_update() argument
5281 bool modeset = needs_modeset(&pipe_config->base); in intel_pre_plane_update()
5285 if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config)) in intel_pre_plane_update()
5293 intel_fbc_pre_update(crtc, pipe_config, new_primary_state); in intel_pre_plane_update()
5305 needs_nv12_wa(dev_priv, pipe_config)) { in intel_pre_plane_update()
5320 pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) in intel_pre_plane_update()
5330 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev)) in intel_pre_plane_update()
5337 if (needs_modeset(&pipe_config->base)) in intel_pre_plane_update()
5356 pipe_config); in intel_pre_plane_update()
5357 else if (pipe_config->update_wm_pre) in intel_pre_plane_update()
5501 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config, in ironlake_crtc_enable() argument
5504 struct drm_crtc *crtc = pipe_config->base.crtc; in ironlake_crtc_enable()
5546 intel_encoders_pre_enable(crtc, pipe_config, old_state); in ironlake_crtc_enable()
5564 intel_color_load_luts(&pipe_config->base); in ironlake_crtc_enable()
5568 intel_enable_pipe(pipe_config); in ironlake_crtc_enable()
5571 ironlake_pch_enable(old_intel_state, pipe_config); in ironlake_crtc_enable()
5576 intel_encoders_enable(crtc, pipe_config, old_state); in ironlake_crtc_enable()
5629 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, in haswell_crtc_enable() argument
5632 struct drm_crtc *crtc = pipe_config->base.crtc; in haswell_crtc_enable()
5645 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); in haswell_crtc_enable()
5651 icl_map_plls_to_ports(crtc, pipe_config, old_state); in haswell_crtc_enable()
5653 intel_encoders_pre_enable(crtc, pipe_config, old_state); in haswell_crtc_enable()
5679 intel_color_set_csc(&pipe_config->base); in haswell_crtc_enable()
5698 intel_color_load_luts(&pipe_config->base); in haswell_crtc_enable()
5711 intel_ddi_set_pipe_settings(pipe_config); in haswell_crtc_enable()
5713 intel_ddi_enable_transcoder_func(pipe_config); in haswell_crtc_enable()
5716 dev_priv->display.initial_watermarks(old_intel_state, pipe_config); in haswell_crtc_enable()
5723 intel_enable_pipe(pipe_config); in haswell_crtc_enable()
5726 lpt_pch_enable(old_intel_state, pipe_config); in haswell_crtc_enable()
5729 intel_ddi_set_vc_payload_alloc(pipe_config, true); in haswell_crtc_enable()
5734 intel_encoders_enable(crtc, pipe_config, old_state); in haswell_crtc_enable()
5743 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; in haswell_crtc_enable()
5862 struct intel_crtc_state *pipe_config = crtc->config; in i9xx_pfit_enable() local
5864 if (!pipe_config->gmch_pfit.control) in i9xx_pfit_enable()
5874 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); in i9xx_pfit_enable()
5875 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); in i9xx_pfit_enable()
5984 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config, in valleyview_crtc_enable() argument
5989 struct drm_crtc *crtc = pipe_config->base.crtc; in valleyview_crtc_enable()
6017 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); in valleyview_crtc_enable()
6027 intel_encoders_pre_enable(crtc, pipe_config, old_state); in valleyview_crtc_enable()
6031 intel_color_load_luts(&pipe_config->base); in valleyview_crtc_enable()
6034 pipe_config); in valleyview_crtc_enable()
6035 intel_enable_pipe(pipe_config); in valleyview_crtc_enable()
6040 intel_encoders_enable(crtc, pipe_config, old_state); in valleyview_crtc_enable()
6052 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config, in i9xx_crtc_enable() argument
6057 struct drm_crtc *crtc = pipe_config->base.crtc; in i9xx_crtc_enable()
6081 intel_encoders_pre_enable(crtc, pipe_config, old_state); in i9xx_crtc_enable()
6083 i9xx_enable_pll(intel_crtc, pipe_config); in i9xx_crtc_enable()
6087 intel_color_load_luts(&pipe_config->base); in i9xx_crtc_enable()
6094 intel_enable_pipe(pipe_config); in i9xx_crtc_enable()
6099 intel_encoders_enable(crtc, pipe_config, old_state); in i9xx_crtc_enable()
6371 struct intel_crtc_state *pipe_config) in ironlake_check_fdi_lanes() argument
6374 struct drm_atomic_state *state = pipe_config->base.state; in ironlake_check_fdi_lanes()
6379 pipe_name(pipe), pipe_config->fdi_lanes); in ironlake_check_fdi_lanes()
6380 if (pipe_config->fdi_lanes > 4) { in ironlake_check_fdi_lanes()
6382 pipe_name(pipe), pipe_config->fdi_lanes); in ironlake_check_fdi_lanes()
6387 if (pipe_config->fdi_lanes > 2) { in ironlake_check_fdi_lanes()
6389 pipe_config->fdi_lanes); in ironlake_check_fdi_lanes()
6404 if (pipe_config->fdi_lanes <= 2) in ironlake_check_fdi_lanes()
6415 pipe_name(pipe), pipe_config->fdi_lanes); in ironlake_check_fdi_lanes()
6420 if (pipe_config->fdi_lanes > 2) { in ironlake_check_fdi_lanes()
6422 pipe_name(pipe), pipe_config->fdi_lanes); in ironlake_check_fdi_lanes()
6444 struct intel_crtc_state *pipe_config) in ironlake_fdi_compute_config() argument
6447 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in ironlake_fdi_compute_config()
6459 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); in ironlake_fdi_compute_config()
6464 pipe_config->pipe_bpp); in ironlake_fdi_compute_config()
6466 pipe_config->fdi_lanes = lane; in ironlake_fdi_compute_config()
6468 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, in ironlake_fdi_compute_config()
6469 link_bw, &pipe_config->fdi_m_n, false); in ironlake_fdi_compute_config()
6471 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); in ironlake_fdi_compute_config()
6472 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { in ironlake_fdi_compute_config()
6473 pipe_config->pipe_bpp -= 2*3; in ironlake_fdi_compute_config()
6475 pipe_config->pipe_bpp); in ironlake_fdi_compute_config()
6477 pipe_config->bw_constrained = true; in ironlake_fdi_compute_config()
6551 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) in ilk_pipe_pixel_rate() argument
6555 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock; in ilk_pipe_pixel_rate()
6562 if (pipe_config->pch_pfit.enabled) { in ilk_pipe_pixel_rate()
6564 uint32_t pfit_size = pipe_config->pch_pfit.size; in ilk_pipe_pixel_rate()
6566 pipe_w = pipe_config->pipe_src_w; in ilk_pipe_pixel_rate()
6567 pipe_h = pipe_config->pipe_src_h; in ilk_pipe_pixel_rate()
6600 struct intel_crtc_state *pipe_config) in intel_crtc_compute_config() argument
6604 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_crtc_compute_config()
6617 pipe_config->double_wide = true; in intel_crtc_compute_config()
6624 yesno(pipe_config->double_wide)); in intel_crtc_compute_config()
6628 if (pipe_config->ycbcr420 && pipe_config->base.ctm) { in intel_crtc_compute_config()
6644 if (pipe_config->pipe_src_w & 1) { in intel_crtc_compute_config()
6645 if (pipe_config->double_wide) { in intel_crtc_compute_config()
6650 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && in intel_crtc_compute_config()
6664 intel_crtc_compute_pixel_rate(pipe_config); in intel_crtc_compute_config()
6666 if (pipe_config->has_pch_encoder) in intel_crtc_compute_config()
6667 return ironlake_fdi_compute_config(crtc, pipe_config); in intel_crtc_compute_config()
6868 struct intel_crtc_state *pipe_config) in vlv_compute_dpll() argument
6870 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | in vlv_compute_dpll()
6873 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in vlv_compute_dpll()
6876 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) in vlv_compute_dpll()
6877 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | in vlv_compute_dpll()
6880 pipe_config->dpll_hw_state.dpll_md = in vlv_compute_dpll()
6881 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; in vlv_compute_dpll()
6885 struct intel_crtc_state *pipe_config) in chv_compute_dpll() argument
6887 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | in chv_compute_dpll()
6890 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in chv_compute_dpll()
6893 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) in chv_compute_dpll()
6894 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; in chv_compute_dpll()
6896 pipe_config->dpll_hw_state.dpll_md = in chv_compute_dpll()
6897 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; in chv_compute_dpll()
6901 const struct intel_crtc_state *pipe_config) in vlv_prepare_pll() argument
6912 pipe_config->dpll_hw_state.dpll & in vlv_prepare_pll()
6916 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in vlv_prepare_pll()
6921 bestn = pipe_config->dpll.n; in vlv_prepare_pll()
6922 bestm1 = pipe_config->dpll.m1; in vlv_prepare_pll()
6923 bestm2 = pipe_config->dpll.m2; in vlv_prepare_pll()
6924 bestp1 = pipe_config->dpll.p1; in vlv_prepare_pll()
6925 bestp2 = pipe_config->dpll.p2; in vlv_prepare_pll()
6962 if (pipe_config->port_clock == 162000 || in vlv_prepare_pll()
6971 if (intel_crtc_has_dp_encoder(pipe_config)) { in vlv_prepare_pll()
7000 const struct intel_crtc_state *pipe_config) in chv_prepare_pll() argument
7013 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); in chv_prepare_pll()
7016 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in chv_prepare_pll()
7019 bestn = pipe_config->dpll.n; in chv_prepare_pll()
7020 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; in chv_prepare_pll()
7021 bestm1 = pipe_config->dpll.m1; in chv_prepare_pll()
7022 bestm2 = pipe_config->dpll.m2 >> 22; in chv_prepare_pll()
7023 bestp1 = pipe_config->dpll.p1; in chv_prepare_pll()
7024 bestp2 = pipe_config->dpll.p2; in chv_prepare_pll()
7025 vco = pipe_config->dpll.vco; in chv_prepare_pll()
7118 struct intel_crtc_state *pipe_config; in vlv_force_pll_on() local
7120 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); in vlv_force_pll_on()
7121 if (!pipe_config) in vlv_force_pll_on()
7124 pipe_config->base.crtc = &crtc->base; in vlv_force_pll_on()
7125 pipe_config->pixel_multiplier = 1; in vlv_force_pll_on()
7126 pipe_config->dpll = *dpll; in vlv_force_pll_on()
7129 chv_compute_dpll(crtc, pipe_config); in vlv_force_pll_on()
7130 chv_prepare_pll(crtc, pipe_config); in vlv_force_pll_on()
7131 chv_enable_pll(crtc, pipe_config); in vlv_force_pll_on()
7133 vlv_compute_dpll(crtc, pipe_config); in vlv_force_pll_on()
7134 vlv_prepare_pll(crtc, pipe_config); in vlv_force_pll_on()
7135 vlv_enable_pll(crtc, pipe_config); in vlv_force_pll_on()
7138 kfree(pipe_config); in vlv_force_pll_on()
7346 struct intel_crtc_state *pipe_config) in intel_get_pipe_timings() argument
7350 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; in intel_get_pipe_timings()
7354 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
7355 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
7357 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
7358 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
7360 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
7361 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
7364 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
7365 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
7367 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
7368 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
7370 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
7371 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
7374 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; in intel_get_pipe_timings()
7375 pipe_config->base.adjusted_mode.crtc_vtotal += 1; in intel_get_pipe_timings()
7376 pipe_config->base.adjusted_mode.crtc_vblank_end += 1; in intel_get_pipe_timings()
7381 struct intel_crtc_state *pipe_config) in intel_get_pipe_src_size() argument
7388 pipe_config->pipe_src_h = (tmp & 0xffff) + 1; in intel_get_pipe_src_size()
7389 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_src_size()
7391 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; in intel_get_pipe_src_size()
7392 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; in intel_get_pipe_src_size()
7396 struct intel_crtc_state *pipe_config) in intel_mode_from_pipe_config() argument
7398 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; in intel_mode_from_pipe_config()
7399 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; in intel_mode_from_pipe_config()
7400 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; in intel_mode_from_pipe_config()
7401 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; in intel_mode_from_pipe_config()
7403 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; in intel_mode_from_pipe_config()
7404 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; in intel_mode_from_pipe_config()
7405 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; in intel_mode_from_pipe_config()
7406 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; in intel_mode_from_pipe_config()
7408 mode->flags = pipe_config->base.adjusted_mode.flags; in intel_mode_from_pipe_config()
7411 mode->clock = pipe_config->base.adjusted_mode.crtc_clock; in intel_mode_from_pipe_config()
7663 struct intel_crtc_state *pipe_config) in i9xx_get_pfit_config() argument
7685 pipe_config->gmch_pfit.control = tmp; in i9xx_get_pfit_config()
7686 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); in i9xx_get_pfit_config()
7690 struct intel_crtc_state *pipe_config) in vlv_crtc_clock_get() argument
7694 int pipe = pipe_config->cpu_transcoder; in vlv_crtc_clock_get()
7700 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in vlv_crtc_clock_get()
7713 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); in vlv_crtc_clock_get()
7793 struct intel_crtc_state *pipe_config) in chv_crtc_clock_get() argument
7797 int pipe = pipe_config->cpu_transcoder; in chv_crtc_clock_get()
7804 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in chv_crtc_clock_get()
7823 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); in chv_crtc_clock_get()
7827 struct intel_crtc_state *pipe_config) in i9xx_get_pipe_config() argument
7838 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; in i9xx_get_pipe_config()
7839 pipe_config->shared_dpll = NULL; in i9xx_get_pipe_config()
7851 pipe_config->pipe_bpp = 18; in i9xx_get_pipe_config()
7854 pipe_config->pipe_bpp = 24; in i9xx_get_pipe_config()
7857 pipe_config->pipe_bpp = 30; in i9xx_get_pipe_config()
7866 pipe_config->limited_color_range = true; in i9xx_get_pipe_config()
7869 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; in i9xx_get_pipe_config()
7871 intel_get_pipe_timings(crtc, pipe_config); in i9xx_get_pipe_config()
7872 intel_get_pipe_src_size(crtc, pipe_config); in i9xx_get_pipe_config()
7874 i9xx_get_pfit_config(crtc, pipe_config); in i9xx_get_pipe_config()
7882 pipe_config->pixel_multiplier = in i9xx_get_pipe_config()
7885 pipe_config->dpll_hw_state.dpll_md = tmp; in i9xx_get_pipe_config()
7889 pipe_config->pixel_multiplier = in i9xx_get_pipe_config()
7896 pipe_config->pixel_multiplier = 1; in i9xx_get_pipe_config()
7898 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); in i9xx_get_pipe_config()
7906 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; in i9xx_get_pipe_config()
7908 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); in i9xx_get_pipe_config()
7909 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); in i9xx_get_pipe_config()
7912 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | in i9xx_get_pipe_config()
7918 chv_crtc_clock_get(crtc, pipe_config); in i9xx_get_pipe_config()
7920 vlv_crtc_clock_get(crtc, pipe_config); in i9xx_get_pipe_config()
7922 i9xx_crtc_clock_get(crtc, pipe_config); in i9xx_get_pipe_config()
7929 pipe_config->base.adjusted_mode.crtc_clock = in i9xx_get_pipe_config()
7930 pipe_config->port_clock / pipe_config->pixel_multiplier; in i9xx_get_pipe_config()
8701 struct intel_crtc_state *pipe_config) in intel_dp_get_m_n() argument
8703 if (pipe_config->has_pch_encoder) in intel_dp_get_m_n()
8704 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); in intel_dp_get_m_n()
8706 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, in intel_dp_get_m_n()
8707 &pipe_config->dp_m_n, in intel_dp_get_m_n()
8708 &pipe_config->dp_m2_n2); in intel_dp_get_m_n()
8712 struct intel_crtc_state *pipe_config) in ironlake_get_fdi_m_n_config() argument
8714 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, in ironlake_get_fdi_m_n_config()
8715 &pipe_config->fdi_m_n, NULL); in ironlake_get_fdi_m_n_config()
8719 struct intel_crtc_state *pipe_config) in skylake_get_pfit_config() argument
8723 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; in skylake_get_pfit_config()
8733 pipe_config->pch_pfit.enabled = true; in skylake_get_pfit_config()
8734 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); in skylake_get_pfit_config()
8735 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); in skylake_get_pfit_config()
8852 struct intel_crtc_state *pipe_config) in ironlake_get_pfit_config() argument
8861 pipe_config->pch_pfit.enabled = true; in ironlake_get_pfit_config()
8862 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); in ironlake_get_pfit_config()
8863 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); in ironlake_get_pfit_config()
8876 struct intel_crtc_state *pipe_config) in ironlake_get_pipe_config() argument
8888 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; in ironlake_get_pipe_config()
8889 pipe_config->shared_dpll = NULL; in ironlake_get_pipe_config()
8898 pipe_config->pipe_bpp = 18; in ironlake_get_pipe_config()
8901 pipe_config->pipe_bpp = 24; in ironlake_get_pipe_config()
8904 pipe_config->pipe_bpp = 30; in ironlake_get_pipe_config()
8907 pipe_config->pipe_bpp = 36; in ironlake_get_pipe_config()
8914 pipe_config->limited_color_range = true; in ironlake_get_pipe_config()
8920 pipe_config->has_pch_encoder = true; in ironlake_get_pipe_config()
8923 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> in ironlake_get_pipe_config()
8926 ironlake_get_fdi_m_n_config(crtc, pipe_config); in ironlake_get_pipe_config()
8942 pipe_config->shared_dpll = in ironlake_get_pipe_config()
8944 pll = pipe_config->shared_dpll; in ironlake_get_pipe_config()
8947 &pipe_config->dpll_hw_state)); in ironlake_get_pipe_config()
8949 tmp = pipe_config->dpll_hw_state.dpll; in ironlake_get_pipe_config()
8950 pipe_config->pixel_multiplier = in ironlake_get_pipe_config()
8954 ironlake_pch_clock_get(crtc, pipe_config); in ironlake_get_pipe_config()
8956 pipe_config->pixel_multiplier = 1; in ironlake_get_pipe_config()
8959 intel_get_pipe_timings(crtc, pipe_config); in ironlake_get_pipe_config()
8960 intel_get_pipe_src_size(crtc, pipe_config); in ironlake_get_pipe_config()
8962 ironlake_get_pfit_config(crtc, pipe_config); in ironlake_get_pipe_config()
9214 struct intel_crtc_state *pipe_config) in cannonlake_get_ddi_pll() argument
9225 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); in cannonlake_get_ddi_pll()
9230 struct intel_crtc_state *pipe_config) in icelake_get_ddi_pll() argument
9263 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); in icelake_get_ddi_pll()
9268 struct intel_crtc_state *pipe_config) in bxt_get_ddi_pll() argument
9287 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); in bxt_get_ddi_pll()
9292 struct intel_crtc_state *pipe_config) in skylake_get_ddi_pll() argument
9303 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); in skylake_get_ddi_pll()
9308 struct intel_crtc_state *pipe_config) in haswell_get_ddi_pll() argument
9339 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); in haswell_get_ddi_pll()
9343 struct intel_crtc_state *pipe_config, in hsw_get_transcoder_state() argument
9355 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; in hsw_get_transcoder_state()
9381 pipe_config->cpu_transcoder = TRANSCODER_EDP; in hsw_get_transcoder_state()
9384 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); in hsw_get_transcoder_state()
9389 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); in hsw_get_transcoder_state()
9395 struct intel_crtc_state *pipe_config, in bxt_get_dsi_transcoder_state() argument
9435 pipe_config->cpu_transcoder = cpu_transcoder; in bxt_get_dsi_transcoder_state()
9439 return transcoder_is_dsi(pipe_config->cpu_transcoder); in bxt_get_dsi_transcoder_state()
9443 struct intel_crtc_state *pipe_config) in haswell_get_ddi_port_state() argument
9450 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); in haswell_get_ddi_port_state()
9455 icelake_get_ddi_pll(dev_priv, port, pipe_config); in haswell_get_ddi_port_state()
9457 cannonlake_get_ddi_pll(dev_priv, port, pipe_config); in haswell_get_ddi_port_state()
9459 skylake_get_ddi_pll(dev_priv, port, pipe_config); in haswell_get_ddi_port_state()
9461 bxt_get_ddi_pll(dev_priv, port, pipe_config); in haswell_get_ddi_port_state()
9463 haswell_get_ddi_pll(dev_priv, port, pipe_config); in haswell_get_ddi_port_state()
9465 pll = pipe_config->shared_dpll; in haswell_get_ddi_port_state()
9468 &pipe_config->dpll_hw_state)); in haswell_get_ddi_port_state()
9478 pipe_config->has_pch_encoder = true; in haswell_get_ddi_port_state()
9481 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> in haswell_get_ddi_port_state()
9484 ironlake_get_fdi_m_n_config(crtc, pipe_config); in haswell_get_ddi_port_state()
9489 struct intel_crtc_state *pipe_config) in haswell_get_pipe_config() argument
9496 intel_crtc_init_scalers(crtc, pipe_config); in haswell_get_pipe_config()
9503 pipe_config->shared_dpll = NULL; in haswell_get_pipe_config()
9505 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); in haswell_get_pipe_config()
9508 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) { in haswell_get_pipe_config()
9516 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { in haswell_get_pipe_config()
9517 haswell_get_ddi_port_state(crtc, pipe_config); in haswell_get_pipe_config()
9518 intel_get_pipe_timings(crtc, pipe_config); in haswell_get_pipe_config()
9521 intel_get_pipe_src_size(crtc, pipe_config); in haswell_get_pipe_config()
9523 pipe_config->gamma_mode = in haswell_get_pipe_config()
9534 pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE; in haswell_get_pipe_config()
9535 if (pipe_config->ycbcr420 != clrspace_yuv || in haswell_get_pipe_config()
9536 pipe_config->ycbcr420 != blend_mode_420) in haswell_get_pipe_config()
9547 skylake_get_pfit_config(crtc, pipe_config); in haswell_get_pipe_config()
9549 ironlake_get_pfit_config(crtc, pipe_config); in haswell_get_pipe_config()
9554 pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE; in haswell_get_pipe_config()
9561 pipe_config->ips_enabled = true; in haswell_get_pipe_config()
9565 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && in haswell_get_pipe_config()
9566 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { in haswell_get_pipe_config()
9567 pipe_config->pixel_multiplier = in haswell_get_pipe_config()
9568 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; in haswell_get_pipe_config()
9570 pipe_config->pixel_multiplier = 1; in haswell_get_pipe_config()
10275 const struct intel_crtc_state *pipe_config) in i9xx_pll_refclk() argument
10278 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_pll_refclk()
10292 struct intel_crtc_state *pipe_config) in i9xx_crtc_clock_get() argument
10296 int pipe = pipe_config->cpu_transcoder; in i9xx_crtc_clock_get()
10297 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_crtc_clock_get()
10301 int refclk = i9xx_pll_refclk(dev, pipe_config); in i9xx_crtc_clock_get()
10304 fp = pipe_config->dpll_hw_state.fp0; in i9xx_crtc_clock_get()
10306 fp = pipe_config->dpll_hw_state.fp1; in i9xx_crtc_clock_get()
10377 pipe_config->port_clock = port_clock; in i9xx_crtc_clock_get()
10400 struct intel_crtc_state *pipe_config) in ironlake_pch_clock_get() argument
10405 i9xx_crtc_clock_get(crtc, pipe_config); in ironlake_pch_clock_get()
10412 pipe_config->base.adjusted_mode.crtc_clock = in ironlake_pch_clock_get()
10413 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), in ironlake_pch_clock_get()
10414 &pipe_config->fdi_m_n); in ironlake_pch_clock_get()
10516 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); in intel_plane_atomic_calc_changes() local
10562 pipe_config->fb_changed = true; in intel_plane_atomic_calc_changes()
10579 pipe_config->update_wm_pre = true; in intel_plane_atomic_calc_changes()
10583 pipe_config->disable_cxsr = true; in intel_plane_atomic_calc_changes()
10586 pipe_config->update_wm_post = true; in intel_plane_atomic_calc_changes()
10590 pipe_config->disable_cxsr = true; in intel_plane_atomic_calc_changes()
10594 pipe_config->update_wm_pre = true; in intel_plane_atomic_calc_changes()
10595 pipe_config->update_wm_post = true; in intel_plane_atomic_calc_changes()
10600 pipe_config->fb_bits |= plane->frontbuffer_bit; in intel_plane_atomic_calc_changes()
10611 pipe_config->disable_lp_wm = true; in intel_plane_atomic_calc_changes()
10652 struct intel_crtc_state *pipe_config = in intel_crtc_atomic_check() local
10659 pipe_config->update_wm_post = true; in intel_crtc_atomic_check()
10663 !WARN_ON(pipe_config->shared_dpll)) { in intel_crtc_atomic_check()
10665 pipe_config); in intel_crtc_atomic_check()
10684 ret = dev_priv->display.compute_pipe_wm(pipe_config); in intel_crtc_atomic_check()
10703 pipe_config); in intel_crtc_atomic_check()
10710 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; in intel_crtc_atomic_check()
10715 ret = skl_update_scaler_crtc(pipe_config); in intel_crtc_atomic_check()
10719 pipe_config); in intel_crtc_atomic_check()
10722 pipe_config); in intel_crtc_atomic_check()
10726 pipe_config->ips_enabled = hsw_compute_ips_config(pipe_config); in intel_crtc_atomic_check()
10764 struct intel_crtc_state *pipe_config) in connected_sink_compute_bpp() argument
10767 int bpp = pipe_config->pipe_bpp; in connected_sink_compute_bpp()
10777 pipe_config->pipe_bpp = info->bpc * 3; in connected_sink_compute_bpp()
10784 pipe_config->pipe_bpp = 24; in connected_sink_compute_bpp()
10790 struct intel_crtc_state *pipe_config) in compute_baseline_pipe_bpp() argument
10807 pipe_config->pipe_bpp = bpp; in compute_baseline_pipe_bpp()
10809 state = pipe_config->base.state; in compute_baseline_pipe_bpp()
10817 pipe_config); in compute_baseline_pipe_bpp()
10835 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id, in intel_dump_m_n_config() argument
10891 struct intel_crtc_state *pipe_config, in intel_dump_pipe_config() argument
10905 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types); in intel_dump_pipe_config()
10907 buf, pipe_config->output_types); in intel_dump_pipe_config()
10910 transcoder_name(pipe_config->cpu_transcoder), in intel_dump_pipe_config()
10911 pipe_config->pipe_bpp, pipe_config->dither); in intel_dump_pipe_config()
10913 if (pipe_config->has_pch_encoder) in intel_dump_pipe_config()
10914 intel_dump_m_n_config(pipe_config, "fdi", in intel_dump_pipe_config()
10915 pipe_config->fdi_lanes, in intel_dump_pipe_config()
10916 &pipe_config->fdi_m_n); in intel_dump_pipe_config()
10918 if (pipe_config->ycbcr420) in intel_dump_pipe_config()
10921 if (intel_crtc_has_dp_encoder(pipe_config)) { in intel_dump_pipe_config()
10922 intel_dump_m_n_config(pipe_config, "dp m_n", in intel_dump_pipe_config()
10923 pipe_config->lane_count, &pipe_config->dp_m_n); in intel_dump_pipe_config()
10924 if (pipe_config->has_drrs) in intel_dump_pipe_config()
10925 intel_dump_m_n_config(pipe_config, "dp m2_n2", in intel_dump_pipe_config()
10926 pipe_config->lane_count, in intel_dump_pipe_config()
10927 &pipe_config->dp_m2_n2); in intel_dump_pipe_config()
10931 pipe_config->has_audio, pipe_config->has_infoframe); in intel_dump_pipe_config()
10934 drm_mode_debug_printmodeline(&pipe_config->base.mode); in intel_dump_pipe_config()
10936 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); in intel_dump_pipe_config()
10937 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); in intel_dump_pipe_config()
10939 pipe_config->port_clock, in intel_dump_pipe_config()
10940 pipe_config->pipe_src_w, pipe_config->pipe_src_h, in intel_dump_pipe_config()
10941 pipe_config->pixel_rate); in intel_dump_pipe_config()
10946 pipe_config->scaler_state.scaler_users, in intel_dump_pipe_config()
10947 pipe_config->scaler_state.scaler_id); in intel_dump_pipe_config()
10951 pipe_config->gmch_pfit.control, in intel_dump_pipe_config()
10952 pipe_config->gmch_pfit.pgm_ratios, in intel_dump_pipe_config()
10953 pipe_config->gmch_pfit.lvds_border_bits); in intel_dump_pipe_config()
10956 pipe_config->pch_pfit.pos, in intel_dump_pipe_config()
10957 pipe_config->pch_pfit.size, in intel_dump_pipe_config()
10958 enableddisabled(pipe_config->pch_pfit.enabled)); in intel_dump_pipe_config()
10961 pipe_config->ips_enabled, pipe_config->double_wide); in intel_dump_pipe_config()
10963 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); in intel_dump_pipe_config()
11103 struct intel_crtc_state *pipe_config) in intel_modeset_pipe_config() argument
11105 struct drm_atomic_state *state = pipe_config->base.state; in intel_modeset_pipe_config()
11113 clear_intel_crtc_state(pipe_config); in intel_modeset_pipe_config()
11115 pipe_config->cpu_transcoder = in intel_modeset_pipe_config()
11123 if (!(pipe_config->base.adjusted_mode.flags & in intel_modeset_pipe_config()
11125 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; in intel_modeset_pipe_config()
11127 if (!(pipe_config->base.adjusted_mode.flags & in intel_modeset_pipe_config()
11129 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; in intel_modeset_pipe_config()
11132 pipe_config); in intel_modeset_pipe_config()
11144 drm_mode_get_hv_timing(&pipe_config->base.mode, in intel_modeset_pipe_config()
11145 &pipe_config->pipe_src_w, in intel_modeset_pipe_config()
11146 &pipe_config->pipe_src_h); in intel_modeset_pipe_config()
11164 pipe_config->output_types |= in intel_modeset_pipe_config()
11165 BIT(encoder->compute_output_type(encoder, pipe_config, in intel_modeset_pipe_config()
11168 pipe_config->output_types |= BIT(encoder->type); in intel_modeset_pipe_config()
11173 pipe_config->port_clock = 0; in intel_modeset_pipe_config()
11174 pipe_config->pixel_multiplier = 1; in intel_modeset_pipe_config()
11177 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, in intel_modeset_pipe_config()
11190 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) { in intel_modeset_pipe_config()
11198 if (!pipe_config->port_clock) in intel_modeset_pipe_config()
11199 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock in intel_modeset_pipe_config()
11200 * pipe_config->pixel_multiplier; in intel_modeset_pipe_config()
11202 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); in intel_modeset_pipe_config()
11223 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) && in intel_modeset_pipe_config()
11224 !pipe_config->dither_force_disable; in intel_modeset_pipe_config()
11226 base_bpp, pipe_config->pipe_bpp, pipe_config->dither); in intel_modeset_pipe_config()
11321 struct intel_crtc_state *pipe_config, in intel_pipe_config_compare() argument
11327 !(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED); in intel_pipe_config_compare()
11330 if (current_config->name != pipe_config->name) { \ in intel_pipe_config_compare()
11334 pipe_config->name); \ in intel_pipe_config_compare()
11340 if (current_config->name != pipe_config->name) { \ in intel_pipe_config_compare()
11344 pipe_config->name); \ in intel_pipe_config_compare()
11350 if (current_config->name != pipe_config->name) { \ in intel_pipe_config_compare()
11354 yesno(pipe_config->name)); \ in intel_pipe_config_compare()
11365 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \ in intel_pipe_config_compare()
11371 yesno(pipe_config->name)); \ in intel_pipe_config_compare()
11377 if (current_config->name != pipe_config->name) { \ in intel_pipe_config_compare()
11381 pipe_config->name); \ in intel_pipe_config_compare()
11388 &pipe_config->name,\ in intel_pipe_config_compare()
11398 pipe_config->name.tu, \ in intel_pipe_config_compare()
11399 pipe_config->name.gmch_m, \ in intel_pipe_config_compare()
11400 pipe_config->name.gmch_n, \ in intel_pipe_config_compare()
11401 pipe_config->name.link_m, \ in intel_pipe_config_compare()
11402 pipe_config->name.link_n); \ in intel_pipe_config_compare()
11414 &pipe_config->name, adjust) && \ in intel_pipe_config_compare()
11416 &pipe_config->name, adjust)) { \ in intel_pipe_config_compare()
11431 pipe_config->name.tu, \ in intel_pipe_config_compare()
11432 pipe_config->name.gmch_m, \ in intel_pipe_config_compare()
11433 pipe_config->name.gmch_n, \ in intel_pipe_config_compare()
11434 pipe_config->name.link_m, \ in intel_pipe_config_compare()
11435 pipe_config->name.link_n); \ in intel_pipe_config_compare()
11441 if ((current_config->name ^ pipe_config->name) & (mask)) { \ in intel_pipe_config_compare()
11446 pipe_config->name & (mask)); \ in intel_pipe_config_compare()
11452 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ in intel_pipe_config_compare()
11456 pipe_config->name); \ in intel_pipe_config_compare()
11462 ((current_config->quirks | pipe_config->quirks) & (quirk)) in intel_pipe_config_compare()
11603 const struct intel_crtc_state *pipe_config) in intel_pipe_config_sanity_check() argument
11605 if (pipe_config->has_pch_encoder) { in intel_pipe_config_sanity_check()
11606 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), in intel_pipe_config_sanity_check()
11607 &pipe_config->fdi_m_n); in intel_pipe_config_sanity_check()
11608 int dotclock = pipe_config->base.adjusted_mode.crtc_clock; in intel_pipe_config_sanity_check()
11826 struct intel_crtc_state *pipe_config, *sw_config; in verify_crtc_state() local
11832 pipe_config = to_intel_crtc_state(old_crtc_state); in verify_crtc_state()
11833 memset(pipe_config, 0, sizeof(*pipe_config)); in verify_crtc_state()
11834 pipe_config->base.crtc = crtc; in verify_crtc_state()
11835 pipe_config->base.state = old_state; in verify_crtc_state()
11839 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); in verify_crtc_state()
11866 encoder->get_config(encoder, pipe_config); in verify_crtc_state()
11869 intel_crtc_compute_pixel_rate(pipe_config); in verify_crtc_state()
11874 intel_pipe_config_sanity_check(dev_priv, pipe_config); in verify_crtc_state()
11878 pipe_config, false)) { in verify_crtc_state()
11880 intel_dump_pipe_config(intel_crtc, pipe_config, in verify_crtc_state()
12128 struct intel_crtc_state *pipe_config; in haswell_mode_set_planes_workaround() local
12130 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); in haswell_mode_set_planes_workaround()
12131 if (IS_ERR(pipe_config)) in haswell_mode_set_planes_workaround()
12132 return PTR_ERR(pipe_config); in haswell_mode_set_planes_workaround()
12134 pipe_config->hsw_workaround_pipe = INVALID_PIPE; in haswell_mode_set_planes_workaround()
12136 if (!pipe_config->base.active || in haswell_mode_set_planes_workaround()
12137 needs_modeset(&pipe_config->base)) in haswell_mode_set_planes_workaround()
12327 struct intel_crtc_state *pipe_config = in intel_atomic_check() local
12338 ret = intel_modeset_pipe_config(crtc, pipe_config); in intel_atomic_check()
12341 pipe_config, "[failed]"); in intel_atomic_check()
12348 pipe_config, true)) { in intel_atomic_check()
12350 pipe_config->update_pipe = true; in intel_atomic_check()
12356 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, in intel_atomic_check()
12402 struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state); in intel_update_crtc() local
12410 dev_priv->display.crtc_enable(pipe_config, state); in intel_update_crtc()
12416 pipe_config); in intel_update_crtc()
12420 intel_fbc_enable(intel_crtc, pipe_config, new_plane_state); in intel_update_crtc()