1552 		   struct intel_crtc_state *pipe_config)  in intel_dp_set_clock()  argument
1574 			if (pipe_config->port_clock == divisor[i].clock) {  in intel_dp_set_clock()
1575 				pipe_config->dpll = divisor[i].dpll;  in intel_dp_set_clock()
1576 				pipe_config->clock_set = true;  in intel_dp_set_clock()
1663 				struct intel_crtc_state *pipe_config)  in intel_dp_compute_bpp()  argument
1669 	bpp = pipe_config->pipe_bpp;  in intel_dp_compute_bpp()
1691 				  struct intel_crtc_state *pipe_config,  in intel_dp_adjust_compliance_config()  argument
1699 		pipe_config->dither_force_disable = bpp == 6 * 3;  in intel_dp_adjust_compliance_config()
1727 				  struct intel_crtc_state *pipe_config,  in intel_dp_compute_link_config_wide()  argument
1730 	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;  in intel_dp_compute_link_config_wide()
1747 					pipe_config->lane_count = lane_count;  in intel_dp_compute_link_config_wide()
1748 					pipe_config->pipe_bpp = bpp;  in intel_dp_compute_link_config_wide()
1749 					pipe_config->port_clock = link_clock;  in intel_dp_compute_link_config_wide()
1762 			     struct intel_crtc_state *pipe_config)  in intel_dp_compute_link_config()  argument
1764 	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;  in intel_dp_compute_link_config()
1782 	limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);  in intel_dp_compute_link_config()
1796 	intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);  in intel_dp_compute_link_config()
1808 	if (!intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits))  in intel_dp_compute_link_config()
1812 		      pipe_config->lane_count, pipe_config->port_clock,  in intel_dp_compute_link_config()
1813 		      pipe_config->pipe_bpp);  in intel_dp_compute_link_config()
1817 					     pipe_config->pipe_bpp),  in intel_dp_compute_link_config()
1818 		      intel_dp_max_data_rate(pipe_config->port_clock,  in intel_dp_compute_link_config()
1819 					     pipe_config->lane_count));  in intel_dp_compute_link_config()
1826 			struct intel_crtc_state *pipe_config,  in intel_dp_compute_config()  argument
1830 	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;  in intel_dp_compute_config()
1833 	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);  in intel_dp_compute_config()
1841 		pipe_config->has_pch_encoder = true;  in intel_dp_compute_config()
1843 	pipe_config->has_drrs = false;  in intel_dp_compute_config()
1845 		pipe_config->has_audio = false;  in intel_dp_compute_config()
1847 		pipe_config->has_audio = intel_dp->has_audio;  in intel_dp_compute_config()
1849 		pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;  in intel_dp_compute_config()
1858 			ret = skl_update_scaler_crtc(pipe_config);  in intel_dp_compute_config()
1864 			intel_gmch_panel_fitting(intel_crtc, pipe_config,  in intel_dp_compute_config()
1867 			intel_pch_panel_fitting(intel_crtc, pipe_config,  in intel_dp_compute_config()
1881 	if (!intel_dp_compute_link_config(encoder, pipe_config))  in intel_dp_compute_config()
1890 		pipe_config->limited_color_range =  in intel_dp_compute_config()
1891 			pipe_config->pipe_bpp != 18 &&  in intel_dp_compute_config()
1895 		pipe_config->limited_color_range =  in intel_dp_compute_config()
1899 	intel_link_compute_m_n(pipe_config->pipe_bpp, pipe_config->lane_count,  in intel_dp_compute_config()
1901 			       pipe_config->port_clock,  in intel_dp_compute_config()
1902 			       &pipe_config->dp_m_n,  in intel_dp_compute_config()
1907 			pipe_config->has_drrs = true;  in intel_dp_compute_config()
1908 			intel_link_compute_m_n(pipe_config->pipe_bpp,  in intel_dp_compute_config()
1909 					       pipe_config->lane_count,  in intel_dp_compute_config()
1911 					       pipe_config->port_clock,  in intel_dp_compute_config()
1912 					       &pipe_config->dp_m2_n2,  in intel_dp_compute_config()
1917 		intel_dp_set_clock(encoder, pipe_config);  in intel_dp_compute_config()
1919 	intel_psr_compute_config(intel_dp, pipe_config);  in intel_dp_compute_config()
1935 			     const struct intel_crtc_state *pipe_config)  in intel_dp_prepare()  argument
1940 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);  in intel_dp_prepare()
1941 	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;  in intel_dp_prepare()
1943 	intel_dp_set_link_params(intel_dp, pipe_config->port_clock,  in intel_dp_prepare()
1944 				 pipe_config->lane_count,  in intel_dp_prepare()
1945 				 intel_crtc_has_type(pipe_config,  in intel_dp_prepare()
1972 	intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);  in intel_dp_prepare()
1999 		if (IS_G4X(dev_priv) && pipe_config->limited_color_range)  in intel_dp_prepare()
2524 				const struct intel_crtc_state *pipe_config)  in ironlake_edp_pll_on()  argument
2526 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);  in ironlake_edp_pll_on()
2534 		      pipe_config->port_clock);  in ironlake_edp_pll_on()
2538 	if (pipe_config->port_clock == 162000)  in ironlake_edp_pll_on()
2702 				struct intel_crtc_state *pipe_config)  in intel_dp_get_config()  argument
2708 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);  in intel_dp_get_config()
2711 		pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);  in intel_dp_get_config()
2713 		pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);  in intel_dp_get_config()
2717 	pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;  in intel_dp_get_config()
2743 	pipe_config->base.adjusted_mode.flags |= flags;  in intel_dp_get_config()
2746 		pipe_config->limited_color_range = true;  in intel_dp_get_config()
2748 	pipe_config->lane_count =  in intel_dp_get_config()
2751 	intel_dp_get_m_n(crtc, pipe_config);  in intel_dp_get_config()
2755 			pipe_config->port_clock = 162000;  in intel_dp_get_config()
2757 			pipe_config->port_clock = 270000;  in intel_dp_get_config()
2760 	pipe_config->base.adjusted_mode.crtc_clock =  in intel_dp_get_config()
2761 		intel_dotclock_calculate(pipe_config->port_clock,  in intel_dp_get_config()
2762 					 &pipe_config->dp_m_n);  in intel_dp_get_config()
2765 	    pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {  in intel_dp_get_config()
2780 			      pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);  in intel_dp_get_config()
2781 		dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;  in intel_dp_get_config()
2970 			    const struct intel_crtc_state *pipe_config,  in intel_enable_dp()  argument
2975 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);  in intel_enable_dp()
2985 		vlv_init_panel_power_sequencer(encoder, pipe_config);  in intel_enable_dp()
2987 	intel_dp_enable_port(intel_dp, pipe_config);  in intel_enable_dp()
2999 			lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);  in intel_enable_dp()
3009 	if (pipe_config->has_audio) {  in intel_enable_dp()
3012 		intel_audio_codec_enable(encoder, pipe_config, conn_state);  in intel_enable_dp()
3017 			  const struct intel_crtc_state *pipe_config,  in g4x_enable_dp()  argument
3020 	intel_enable_dp(encoder, pipe_config, conn_state);  in g4x_enable_dp()
3021 	intel_edp_backlight_on(pipe_config, conn_state);  in g4x_enable_dp()
3025 			  const struct intel_crtc_state *pipe_config,  in vlv_enable_dp()  argument
3028 	intel_edp_backlight_on(pipe_config, conn_state);  in vlv_enable_dp()
3032 			      const struct intel_crtc_state *pipe_config,  in g4x_pre_enable_dp()  argument
3038 	intel_dp_prepare(encoder, pipe_config);  in g4x_pre_enable_dp()
3042 		ironlake_edp_pll_on(intel_dp, pipe_config);  in g4x_pre_enable_dp()
3146 			      const struct intel_crtc_state *pipe_config,  in vlv_pre_enable_dp()  argument
3149 	vlv_phy_pre_encoder_enable(encoder, pipe_config);  in vlv_pre_enable_dp()
3151 	intel_enable_dp(encoder, pipe_config, conn_state);  in vlv_pre_enable_dp()
3155 				  const struct intel_crtc_state *pipe_config,  in vlv_dp_pre_pll_enable()  argument
3158 	intel_dp_prepare(encoder, pipe_config);  in vlv_dp_pre_pll_enable()
3160 	vlv_phy_pre_pll_enable(encoder, pipe_config);  in vlv_dp_pre_pll_enable()
3164 			      const struct intel_crtc_state *pipe_config,  in chv_pre_enable_dp()  argument
3167 	chv_phy_pre_encoder_enable(encoder, pipe_config);  in chv_pre_enable_dp()
3169 	intel_enable_dp(encoder, pipe_config, conn_state);  in chv_pre_enable_dp()
3176 				  const struct intel_crtc_state *pipe_config,  in chv_dp_pre_pll_enable()  argument
3179 	intel_dp_prepare(encoder, pipe_config);  in chv_dp_pre_pll_enable()
3181 	chv_phy_pre_pll_enable(encoder, pipe_config);  in chv_dp_pre_pll_enable()