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Searched refs:membase (Results 1 – 25 of 239) sorted by relevance

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/Linux-v4.19/drivers/net/ethernet/allwinner/
Dsun4i-emac.c77 void __iomem *membase; member
99 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
103 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
112 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
116 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
195 writel(0, db->membase + EMAC_CTL_REG); in emac_reset()
197 writel(EMAC_CTL_RESET, db->membase + EMAC_CTL_REG); in emac_reset()
262 reg_val = readl(db->membase + EMAC_TX_MODE_REG); in emac_setup()
265 db->membase + EMAC_TX_MODE_REG); in emac_setup()
269 reg_val = readl(db->membase + EMAC_MAC_CTL0_REG); in emac_setup()
[all …]
/Linux-v4.19/drivers/atm/
Didt77252.h355 void __iomem *membase; /* SAR's memory base address */ member
441 #define SAR_REG_DR0 (card->membase + 0x00)
442 #define SAR_REG_DR1 (card->membase + 0x04)
443 #define SAR_REG_DR2 (card->membase + 0x08)
444 #define SAR_REG_DR3 (card->membase + 0x0C)
445 #define SAR_REG_CMD (card->membase + 0x10)
446 #define SAR_REG_CFG (card->membase + 0x14)
447 #define SAR_REG_STAT (card->membase + 0x18)
448 #define SAR_REG_RSQB (card->membase + 0x1C)
449 #define SAR_REG_RSQT (card->membase + 0x20)
[all …]
/Linux-v4.19/drivers/tty/serial/
Dxilinx_uartps.c220 while ((readl(port->membase + CDNS_UART_SR) & in cdns_uart_handle_rx()
223 rxbs_status = readl(port->membase + CDNS_UART_RXBS); in cdns_uart_handle_rx()
224 data = readl(port->membase + CDNS_UART_FIFO); in cdns_uart_handle_rx()
308 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR); in cdns_uart_handle_tx()
312 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) { in cdns_uart_handle_tx()
320 tail], port->membase + CDNS_UART_FIFO); in cdns_uart_handle_tx()
358 isrstatus = readl(port->membase + CDNS_UART_ISR); in cdns_uart_isr()
359 writel(isrstatus, port->membase + CDNS_UART_ISR); in cdns_uart_isr()
454 mreg = readl(port->membase + CDNS_UART_MR); in cdns_uart_set_baud_rate()
459 writel(mreg, port->membase + CDNS_UART_MR); in cdns_uart_set_baud_rate()
[all …]
Dnetx-serial.c109 val = readl(port->membase + UART_CR); in netx_stop_tx()
110 writel(val & ~CR_TIE, port->membase + UART_CR); in netx_stop_tx()
116 val = readl(port->membase + UART_CR); in netx_stop_rx()
117 writel(val & ~CR_RIE, port->membase + UART_CR); in netx_stop_rx()
123 val = readl(port->membase + UART_CR); in netx_enable_ms()
124 writel(val | CR_MSIE, port->membase + UART_CR); in netx_enable_ms()
132 writel(port->x_char, port->membase + UART_DR); in netx_transmit_buffer()
146 writel(xmit->buf[xmit->tail], port->membase + UART_DR); in netx_transmit_buffer()
152 } while (!(readl(port->membase + UART_FR) & FR_TXFF)); in netx_transmit_buffer()
161 readl(port->membase + UART_CR) | CR_TIE, port->membase + UART_CR); in netx_start_tx()
[all …]
Dmcf.c62 return (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXEMPTY) ? in mcf_tx_empty()
73 sigs = (readb(port->membase + MCFUART_UIPR) & MCFUART_UIPR_CTS) ? in mcf_get_mctrl()
91 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1); in mcf_set_mctrl()
93 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP0); in mcf_set_mctrl()
104 writeb(MCFUART_UCR_TXENABLE, port->membase + MCFUART_UCR); in mcf_start_tx()
106 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1); in mcf_start_tx()
109 writeb(pp->imr, port->membase + MCFUART_UIMR); in mcf_start_tx()
119 writeb(pp->imr, port->membase + MCFUART_UIMR); in mcf_stop_tx()
129 writeb(pp->imr, port->membase + MCFUART_UIMR); in mcf_stop_rx()
140 writeb(MCFUART_UCR_CMDBREAKSTART, port->membase + MCFUART_UCR); in mcf_break_ctl()
[all …]
Dmvebu-uart.c162 st = readl(port->membase + UART_STAT); in mvebu_uart_tx_empty()
184 unsigned int ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
187 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
196 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port)); in mvebu_uart_start_tx()
201 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
203 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
210 ctl = readl(port->membase + UART_CTRL(port)); in mvebu_uart_stop_rx()
212 writel(ctl, port->membase + UART_CTRL(port)); in mvebu_uart_stop_rx()
214 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
216 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
[all …]
Dtimbuart.c42 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~RXFLAGS; in timbuart_stop_rx()
43 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_rx()
49 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~TXBAE; in timbuart_stop_tx()
50 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_tx()
64 u32 isr = ioread32(port->membase + TIMBUART_ISR); in timbuart_tx_empty()
72 u8 ctl = ioread8(port->membase + TIMBUART_CTRL) | in timbuart_flush_buffer()
75 iowrite8(ctl, port->membase + TIMBUART_CTRL); in timbuart_flush_buffer()
76 iowrite32(TXBF, port->membase + TIMBUART_ISR); in timbuart_flush_buffer()
84 while (ioread32(port->membase + TIMBUART_ISR) & RXDP) { in timbuart_rx_chars()
85 u8 ch = ioread8(port->membase + TIMBUART_RXFIFO); in timbuart_rx_chars()
[all …]
Dlpc32xx_hs.c102 port->membase))) == 0) in wait_for_xmit_empty()
116 port->membase))) < 32) in wait_for_xmit_ready()
127 writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase)); in lpc32xx_hsuart_console_putchar()
167 if (!port->membase) in lpc32xx_hsuart_console_setup()
244 while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) && in __serial_uart_flush()
246 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); in __serial_uart_flush()
255 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); in __serial_lpc32xx_rx()
263 LPC32XX_HSUART_IIR(port->membase)); in __serial_lpc32xx_rx()
271 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); in __serial_lpc32xx_rx()
285 writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase)); in __serial_lpc32xx_tx()
[all …]
Dqcom_geni_serial.c204 uport->membase = devm_ioremap_resource(&pdev->dev, res); in qcom_geni_serial_request_port()
205 if (IS_ERR(uport->membase)) in qcom_geni_serial_request_port()
206 return PTR_ERR(uport->membase); in qcom_geni_serial_request_port()
207 port->se.base = uport->membase; in qcom_geni_serial_request_port()
227 geni_ios = readl_relaxed(uport->membase + SE_GENI_IOS); in qcom_geni_serial_get_mctrl()
245 writel_relaxed(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); in qcom_geni_serial_set_mctrl()
296 reg = readl_relaxed(uport->membase + offset); in qcom_geni_serial_poll_bit()
309 writel_relaxed(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN); in qcom_geni_serial_setup_tx()
311 writel(m_cmd, uport->membase + SE_GENI_M_CMD0); in qcom_geni_serial_setup_tx()
322 writel_relaxed(M_GENI_CMD_ABORT, uport->membase + in qcom_geni_serial_poll_tx_done()
[all …]
Dmeson_uart.c96 val = readl(port->membase + AML_UART_STATUS); in meson_uart_tx_empty()
105 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_stop_tx()
107 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_stop_tx()
114 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_stop_rx()
116 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_stop_rx()
128 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_shutdown()
131 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_shutdown()
147 while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) { in meson_uart_start_tx()
149 writel(port->x_char, port->membase + AML_UART_WFIFO); in meson_uart_start_tx()
159 writel(ch, port->membase + AML_UART_WFIFO); in meson_uart_start_tx()
[all …]
Damba-pl010.c69 cr = readb(uap->port.membase + UART010_CR); in pl010_stop_tx()
71 writel(cr, uap->port.membase + UART010_CR); in pl010_stop_tx()
80 cr = readb(uap->port.membase + UART010_CR); in pl010_start_tx()
82 writel(cr, uap->port.membase + UART010_CR); in pl010_start_tx()
91 cr = readb(uap->port.membase + UART010_CR); in pl010_stop_rx()
93 writel(cr, uap->port.membase + UART010_CR); in pl010_stop_rx()
101 cr = readb(uap->port.membase + UART010_CR); in pl010_disable_ms()
103 writel(cr, uap->port.membase + UART010_CR); in pl010_disable_ms()
112 cr = readb(uap->port.membase + UART010_CR); in pl010_enable_ms()
114 writel(cr, uap->port.membase + UART010_CR); in pl010_enable_ms()
[all …]
Dlantiq.c141 ltq_w32(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); in lqasc_stop_rx()
150 fifocnt = ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_RXFFLMASK; in lqasc_rx_chars()
153 ch = ltq_r8(port->membase + LTQ_ASC_RBUF); in lqasc_rx_chars()
154 rsr = (ltq_r32(port->membase + LTQ_ASC_STATE) in lqasc_rx_chars()
167 port->membase + LTQ_ASC_WHBSTATE); in lqasc_rx_chars()
171 port->membase + LTQ_ASC_WHBSTATE); in lqasc_rx_chars()
176 port->membase + LTQ_ASC_WHBSTATE); in lqasc_rx_chars()
214 while (((ltq_r32(port->membase + LTQ_ASC_FSTAT) & in lqasc_tx_chars()
217 ltq_w8(port->x_char, port->membase + LTQ_ASC_TBUF); in lqasc_tx_chars()
227 port->membase + LTQ_ASC_TBUF); in lqasc_tx_chars()
[all …]
Ddigicolor-usart.c85 return !!(readb_relaxed(port->membase + UA_STATUS_FIFO) & in digicolor_uart_tx_full()
91 return !!(readb_relaxed(port->membase + UA_STATUS_FIFO) & in digicolor_uart_rx_empty()
97 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); in digicolor_uart_stop_tx()
100 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); in digicolor_uart_stop_tx()
105 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); in digicolor_uart_start_tx()
108 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); in digicolor_uart_start_tx()
113 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); in digicolor_uart_stop_rx()
116 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); in digicolor_uart_stop_rx()
127 writeb_relaxed(UA_INT_RX, dp->port.membase + UA_INTFLAG_SET); in digicolor_rx_poll()
145 ch = readb_relaxed(port->membase + UA_EMI_REC); in digicolor_uart_rx()
[all …]
Dfsl_lpuart.c294 return readl(port->membase + off); in lpuart32_read()
296 return ioread32be(port->membase + off); in lpuart32_read()
307 writel(val, port->membase + off); in lpuart32_write()
310 iowrite32be(val, port->membase + off); in lpuart32_write()
319 temp = readb(port->membase + UARTCR2); in lpuart_stop_tx()
321 writeb(temp, port->membase + UARTCR2); in lpuart_stop_tx()
337 temp = readb(port->membase + UARTCR2); in lpuart_stop_rx()
338 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); in lpuart_stop_rx()
476 writeb(0, sport->port.membase + UARTCR2); in lpuart_poll_init()
478 temp = readb(sport->port.membase + UARTPFIFO); in lpuart_poll_init()
[all …]
Daltera_jtaguart.c64 return (readl(port->membase + ALTERA_JTAGUART_CONTROL_REG) & in altera_jtaguart_tx_empty()
83 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG); in altera_jtaguart_start_tx()
92 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG); in altera_jtaguart_stop_tx()
101 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG); in altera_jtaguart_stop_rx()
123 while ((status = readl(port->membase + ALTERA_JTAGUART_DATA_REG)) & in altera_jtaguart_rx_chars()
147 writel(port->x_char, port->membase + ALTERA_JTAGUART_DATA_REG); in altera_jtaguart_tx_chars()
155 count = (readl(port->membase + ALTERA_JTAGUART_CONTROL_REG) & in altera_jtaguart_tx_chars()
164 port->membase + ALTERA_JTAGUART_DATA_REG); in altera_jtaguart_tx_chars()
175 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG); in altera_jtaguart_tx_chars()
186 isr = (readl(port->membase + ALTERA_JTAGUART_CONTROL_REG) >> in altera_jtaguart_interrupt()
[all …]
/Linux-v4.19/drivers/isdn/hisax/
Dtelespci.c183 return (readisac(cs->hw.teles0.membase, offset)); in ReadISAC()
189 writeisac(cs->hw.teles0.membase, offset, value); in WriteISAC()
195 read_fifo_isac(cs->hw.teles0.membase, data, size); in ReadISACfifo()
201 write_fifo_isac(cs->hw.teles0.membase, data, size); in WriteISACfifo()
207 return (readhscx(cs->hw.teles0.membase, hscx, offset)); in ReadHSCX()
213 writehscx(cs->hw.teles0.membase, hscx, offset, value); in WriteHSCX()
220 #define READHSCX(cs, nr, reg) readhscx(cs->hw.teles0.membase, nr, reg)
221 #define WRITEHSCX(cs, nr, reg, data) writehscx(cs->hw.teles0.membase, nr, reg, data)
222 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt)
223 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt)
[all …]
Dteles0.c100 return (readisac(cs->hw.teles0.membase, offset)); in ReadISAC()
106 writeisac(cs->hw.teles0.membase, offset, value); in WriteISAC()
112 read_fifo_isac(cs->hw.teles0.membase, data, size); in ReadISACfifo()
118 write_fifo_isac(cs->hw.teles0.membase, data, size); in WriteISACfifo()
124 return (readhscx(cs->hw.teles0.membase, hscx, offset)); in ReadHSCX()
130 writehscx(cs->hw.teles0.membase, hscx, offset, value); in WriteHSCX()
137 #define READHSCX(cs, nr, reg) readhscx(cs->hw.teles0.membase, nr, reg)
138 #define WRITEHSCX(cs, nr, reg, data) writehscx(cs->hw.teles0.membase, nr, reg, data)
139 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt)
140 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt)
[all …]
/Linux-v4.19/drivers/gpio/
Dgpio-timberdale.c47 void __iomem *membase; member
61 reg = ioread32(tgpio->membase + offset); in timbgpio_update_bit()
68 iowrite32(reg, tgpio->membase + offset); in timbgpio_update_bit()
84 value = ioread32(tgpio->membase + TGPIOVAL); in timbgpio_gpio_get()
121 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER); in timbgpio_irq_disable()
133 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER); in timbgpio_irq_enable()
149 ver = ioread32(tgpio->membase + TGPIO_VER); in timbgpio_irq_type()
153 lvr = ioread32(tgpio->membase + TGPIO_LVR); in timbgpio_irq_type()
154 flr = ioread32(tgpio->membase + TGPIO_FLR); in timbgpio_irq_type()
156 bflr = ioread32(tgpio->membase + TGPIO_BFLR); in timbgpio_irq_type()
[all …]
Dgpio-sa1100.c21 void __iomem *membase; member
44 return readl_relaxed(sa1100_gpio_chip(chip)->membase + R_GPLR) & in sa1100_gpio_get()
52 writel_relaxed(BIT(offset), sa1100_gpio_chip(chip)->membase + reg); in sa1100_gpio_set()
57 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR; in sa1100_get_direction()
64 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR; in sa1100_direction_input()
76 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR; in sa1100_direction_output()
104 .membase = (void *)&GPLR,
115 void *base = sgc->membase; in sa1100_update_edge_regs()
157 writel_relaxed(BIT(d->hwirq), sgc->membase + R_GEDR); in sa1100_gpio_ack()
233 void __iomem *gedr = sgc->membase + R_GEDR; in sa1100_gpio_handler()
[all …]
/Linux-v4.19/drivers/net/phy/
Dmdio-sun4i.c35 void __iomem *membase; member
46 writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG); in sun4i_mdio_read()
48 writel(0x1, data->membase + EMAC_MAC_MCMD_REG); in sun4i_mdio_read()
52 while (readl(data->membase + EMAC_MAC_MIND_REG) & 0x1) { in sun4i_mdio_read()
59 writel(0x0, data->membase + EMAC_MAC_MCMD_REG); in sun4i_mdio_read()
61 value = readl(data->membase + EMAC_MAC_MRDD_REG); in sun4i_mdio_read()
73 writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG); in sun4i_mdio_write()
75 writel(0x1, data->membase + EMAC_MAC_MCMD_REG); in sun4i_mdio_write()
79 while (readl(data->membase + EMAC_MAC_MIND_REG) & 0x1) { in sun4i_mdio_write()
86 writel(0x0, data->membase + EMAC_MAC_MCMD_REG); in sun4i_mdio_write()
[all …]
/Linux-v4.19/drivers/i2c/busses/
Di2c-uniphier-f.c92 void __iomem *membase; member
120 writel(*priv->buf++, priv->membase + UNIPHIER_FI2C_DTTX); in uniphier_fi2c_fill_txfifo()
134 *priv->buf++ = readl(priv->membase + UNIPHIER_FI2C_DTRX); in uniphier_fi2c_drain_rxfifo()
142 writel(priv->enabled_irqs, priv->membase + UNIPHIER_FI2C_IE); in uniphier_fi2c_set_irqs()
147 writel(-1, priv->membase + UNIPHIER_FI2C_IC); in uniphier_fi2c_clear_irqs()
157 priv->membase + UNIPHIER_FI2C_CR); in uniphier_fi2c_stop()
165 irq_status = readl(priv->membase + UNIPHIER_FI2C_INT); in uniphier_fi2c_interrupt()
226 priv->membase + UNIPHIER_FI2C_CR); in uniphier_fi2c_interrupt()
256 writel(0, priv->membase + UNIPHIER_FI2C_TBC); in uniphier_fi2c_tx_init()
259 priv->membase + UNIPHIER_FI2C_DTTX); in uniphier_fi2c_tx_init()
[all …]
/Linux-v4.19/drivers/reset/
Dreset-stm32mp1.c18 void __iomem *membase; member
36 addr = data->membase + (bank * reg_width); in stm32_reset_update()
66 reg = readl(data->membase + (bank * reg_width)); in stm32_reset_status()
86 void __iomem *membase; in stm32_reset_probe() local
94 membase = devm_ioremap_resource(dev, res); in stm32_reset_probe()
95 if (IS_ERR(membase)) in stm32_reset_probe()
96 return PTR_ERR(membase); in stm32_reset_probe()
98 data->membase = membase; in stm32_reset_probe()
Dreset-simple.c47 reg = readl(data->membase + (bank * reg_width)); in reset_simple_update()
52 writel(reg, data->membase + (bank * reg_width)); in reset_simple_update()
80 reg = readl(data->membase + (bank * reg_width)); in reset_simple_status()
139 void __iomem *membase; in reset_simple_probe() local
150 membase = devm_ioremap_resource(dev, res); in reset_simple_probe()
151 if (IS_ERR(membase)) in reset_simple_probe()
152 return PTR_ERR(membase); in reset_simple_probe()
155 data->membase = membase; in reset_simple_probe()
177 data->membase += reg_offset; in reset_simple_probe()
/Linux-v4.19/drivers/input/keyboard/
Dlocomokbd.c87 static inline void locomokbd_charge_all(unsigned long membase) in locomokbd_charge_all() argument
89 locomo_writel(0x00FF, membase + LOCOMO_KSC); in locomokbd_charge_all()
92 static inline void locomokbd_activate_all(unsigned long membase) in locomokbd_activate_all() argument
96 locomo_writel(0, membase + LOCOMO_KSC); in locomokbd_activate_all()
97 r = locomo_readl(membase + LOCOMO_KIC); in locomokbd_activate_all()
99 locomo_writel(r, membase + LOCOMO_KIC); in locomokbd_activate_all()
102 static inline void locomokbd_activate_col(unsigned long membase, int col) in locomokbd_activate_col() argument
109 locomo_writel(nbset, membase + LOCOMO_KSC); in locomokbd_activate_col()
112 static inline void locomokbd_reset_col(unsigned long membase, int col) in locomokbd_reset_col() argument
117 locomo_writel(nbset, membase + LOCOMO_KSC); in locomokbd_reset_col()
[all …]
/Linux-v4.19/drivers/dma/
Dtimb_dma.c80 void __iomem *membase; member
97 void __iomem *membase; member
126 ier = ioread32(td->membase + TIMBDMA_IER); in __td_enable_chan_irq()
130 iowrite32(ier, td->membase + TIMBDMA_IER); in __td_enable_chan_irq()
144 isr = ioread32(td->membase + TIMBDMA_ISR) & (1 << id); in __td_dma_done_ack()
146 iowrite32(isr, td->membase + TIMBDMA_ISR); in __td_dma_done_ack()
201 td_chan, td_chan->chan.chan_id, td_chan->membase); in __td_start_dma()
206 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_DHAR); in __td_start_dma()
207 iowrite32(td_desc->txd.phys, td_chan->membase + in __td_start_dma()
210 iowrite32(td_chan->bytes_per_line, td_chan->membase + in __td_start_dma()
[all …]

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