204 	uport->membase = devm_ioremap_resource(&pdev->dev, res);  in qcom_geni_serial_request_port()
205 	if (IS_ERR(uport->membase))  in qcom_geni_serial_request_port()
206 		return PTR_ERR(uport->membase);  in qcom_geni_serial_request_port()
207 	port->se.base = uport->membase;  in qcom_geni_serial_request_port()
227 		geni_ios = readl_relaxed(uport->membase + SE_GENI_IOS);  in qcom_geni_serial_get_mctrl()
245 	writel_relaxed(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);  in qcom_geni_serial_set_mctrl()
296 		reg = readl_relaxed(uport->membase + offset);  in qcom_geni_serial_poll_bit()
309 	writel_relaxed(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);  in qcom_geni_serial_setup_tx()
311 	writel(m_cmd, uport->membase + SE_GENI_M_CMD0);  in qcom_geni_serial_setup_tx()
322 		writel_relaxed(M_GENI_CMD_ABORT, uport->membase +  in qcom_geni_serial_poll_tx_done()
328 	writel_relaxed(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);  in qcom_geni_serial_poll_tx_done()
335 	writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);  in qcom_geni_serial_abort_rx()
338 	writel_relaxed(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);  in qcom_geni_serial_abort_rx()
339 	writel_relaxed(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);  in qcom_geni_serial_abort_rx()
348 	status = readl_relaxed(uport->membase + SE_GENI_M_IRQ_STATUS);  in qcom_geni_serial_get_char()
349 	writel_relaxed(status, uport->membase + SE_GENI_M_IRQ_CLEAR);  in qcom_geni_serial_get_char()
351 	status = readl_relaxed(uport->membase + SE_GENI_S_IRQ_STATUS);  in qcom_geni_serial_get_char()
352 	writel_relaxed(status, uport->membase + SE_GENI_S_IRQ_CLEAR);  in qcom_geni_serial_get_char()
360 	status = readl_relaxed(uport->membase + SE_GENI_RX_FIFO_STATUS);  in qcom_geni_serial_get_char()
364 	rx_fifo = readl(uport->membase + SE_GENI_RX_FIFOn);  in qcom_geni_serial_get_char()
373 	writel_relaxed(port->tx_wm, uport->membase + SE_GENI_TX_WATERMARK_REG);  in qcom_geni_serial_poll_put_char()
377 	writel_relaxed(c, uport->membase + SE_GENI_TX_FIFOn);  in qcom_geni_serial_poll_put_char()
378 	writel_relaxed(M_TX_FIFO_WATERMARK_EN, uport->membase +  in qcom_geni_serial_poll_put_char()
387 	writel_relaxed(ch, uport->membase + SE_GENI_TX_FIFOn);  in qcom_geni_serial_wr_char()
406 	writel_relaxed(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);  in __qcom_geni_serial_console_write()
424 		writel_relaxed(M_TX_FIFO_WATERMARK_EN, uport->membase +  in __qcom_geni_serial_console_write()
459 			writel_relaxed(M_CMD_ABORT_EN, uport->membase +  in qcom_geni_serial_console_write()
462 		writel_relaxed(M_CMD_CANCEL_EN, uport->membase +  in qcom_geni_serial_console_write()
483 		ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);  in handle_rx_console()
525 	ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words);  in handle_rx_uart()
553 		status = readl(uport->membase + SE_GENI_STATUS);  in qcom_geni_serial_start_tx()
560 		irq_en = readl_relaxed(uport->membase +	SE_GENI_M_IRQ_EN);  in qcom_geni_serial_start_tx()
563 		writel_relaxed(port->tx_wm, uport->membase +  in qcom_geni_serial_start_tx()
565 		writel_relaxed(irq_en, uport->membase +	SE_GENI_M_IRQ_EN);  in qcom_geni_serial_start_tx()
575 	irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);  in qcom_geni_serial_stop_tx()
579 		writel_relaxed(0, uport->membase +  in qcom_geni_serial_stop_tx()
582 	writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);  in qcom_geni_serial_stop_tx()
583 	status = readl_relaxed(uport->membase + SE_GENI_STATUS);  in qcom_geni_serial_stop_tx()
600 		writel_relaxed(M_CMD_ABORT_EN, uport->membase +  in qcom_geni_serial_stop_tx()
603 	writel_relaxed(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);  in qcom_geni_serial_stop_tx()
612 	status = readl_relaxed(uport->membase + SE_GENI_STATUS);  in qcom_geni_serial_start_rx()
625 		irq_en = readl_relaxed(uport->membase + SE_GENI_S_IRQ_EN);  in qcom_geni_serial_start_rx()
627 		writel_relaxed(irq_en, uport->membase + SE_GENI_S_IRQ_EN);  in qcom_geni_serial_start_rx()
629 		irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);  in qcom_geni_serial_start_rx()
631 		writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);  in qcom_geni_serial_start_rx()
643 		irq_en = readl_relaxed(uport->membase + SE_GENI_S_IRQ_EN);  in qcom_geni_serial_stop_rx()
645 		writel_relaxed(irq_en, uport->membase + SE_GENI_S_IRQ_EN);  in qcom_geni_serial_stop_rx()
647 		irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);  in qcom_geni_serial_stop_rx()
649 		writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);  in qcom_geni_serial_stop_rx()
652 	status = readl_relaxed(uport->membase + SE_GENI_STATUS);  in qcom_geni_serial_stop_rx()
666 	status = readl_relaxed(uport->membase + SE_GENI_STATUS);  in qcom_geni_serial_stop_rx()
667 	writel_relaxed(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);  in qcom_geni_serial_stop_rx()
681 	status = readl_relaxed(uport->membase +	SE_GENI_RX_FIFO_STATUS);  in qcom_geni_serial_handle_rx()
710 	status = readl_relaxed(uport->membase + SE_GENI_TX_FIFO_STATUS);  in qcom_geni_serial_handle_tx()
718 		irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);  in qcom_geni_serial_handle_tx()
720 		writel_relaxed(0, uport->membase + SE_GENI_TX_WATERMARK_REG);  in qcom_geni_serial_handle_tx()
721 		writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);  in qcom_geni_serial_handle_tx()
743 		iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);  in qcom_geni_serial_handle_tx()
774 	m_irq_status = readl_relaxed(uport->membase + SE_GENI_M_IRQ_STATUS);  in qcom_geni_serial_isr()
775 	s_irq_status = readl_relaxed(uport->membase + SE_GENI_S_IRQ_STATUS);  in qcom_geni_serial_isr()
776 	m_irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);  in qcom_geni_serial_isr()
777 	writel_relaxed(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);  in qcom_geni_serial_isr()
778 	writel_relaxed(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);  in qcom_geni_serial_isr()
856 	writel_relaxed(rxstale, uport->membase + SE_UART_RX_STALE_CNT);  in qcom_geni_serial_port_setup()
971 	tx_trans_cfg = readl_relaxed(uport->membase + SE_UART_TX_TRANS_CFG);  in qcom_geni_serial_set_termios()
972 	tx_parity_cfg = readl_relaxed(uport->membase + SE_UART_TX_PARITY_CFG);  in qcom_geni_serial_set_termios()
973 	rx_trans_cfg = readl_relaxed(uport->membase + SE_UART_RX_TRANS_CFG);  in qcom_geni_serial_set_termios()
974 	rx_parity_cfg = readl_relaxed(uport->membase + SE_UART_RX_PARITY_CFG);  in qcom_geni_serial_set_termios()
1031 				uport->membase + SE_UART_LOOPBACK_CFG);  in qcom_geni_serial_set_termios()
1032 	writel_relaxed(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);  in qcom_geni_serial_set_termios()
1033 	writel_relaxed(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);  in qcom_geni_serial_set_termios()
1034 	writel_relaxed(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);  in qcom_geni_serial_set_termios()
1035 	writel_relaxed(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);  in qcom_geni_serial_set_termios()
1036 	writel_relaxed(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);  in qcom_geni_serial_set_termios()
1037 	writel_relaxed(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);  in qcom_geni_serial_set_termios()
1038 	writel_relaxed(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);  in qcom_geni_serial_set_termios()
1039 	writel_relaxed(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);  in qcom_geni_serial_set_termios()
1040 	writel_relaxed(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);  in qcom_geni_serial_set_termios()
1047 	return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);  in qcom_geni_serial_tx_empty()
1071 	if (unlikely(!uport->membase))  in qcom_geni_console_setup()
1117 	if (!uport->membase)  in qcom_geni_serial_earlycon_setup()
1121 	se.base = uport->membase;  in qcom_geni_serial_earlycon_setup()
1141 	writel_relaxed(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);  in qcom_geni_serial_earlycon_setup()
1142 	writel_relaxed(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);  in qcom_geni_serial_earlycon_setup()
1143 	writel_relaxed(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);  in qcom_geni_serial_earlycon_setup()
1144 	writel_relaxed(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);  in qcom_geni_serial_earlycon_setup()
1145 	writel_relaxed(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);  in qcom_geni_serial_earlycon_setup()
1146 	writel_relaxed(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);  in qcom_geni_serial_earlycon_setup()
1147 	writel_relaxed(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);  in qcom_geni_serial_earlycon_setup()