162 	st = readl(port->membase + UART_STAT);  in mvebu_uart_tx_empty()
184 	unsigned int ctl = readl(port->membase + UART_INTR(port));  in mvebu_uart_stop_tx()
187 	writel(ctl, port->membase + UART_INTR(port));  in mvebu_uart_stop_tx()
196 		writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));  in mvebu_uart_start_tx()
201 	ctl = readl(port->membase + UART_INTR(port));  in mvebu_uart_start_tx()
203 	writel(ctl, port->membase + UART_INTR(port));  in mvebu_uart_start_tx()
210 	ctl = readl(port->membase + UART_CTRL(port));  in mvebu_uart_stop_rx()
212 	writel(ctl, port->membase + UART_CTRL(port));  in mvebu_uart_stop_rx()
214 	ctl = readl(port->membase + UART_INTR(port));  in mvebu_uart_stop_rx()
216 	writel(ctl, port->membase + UART_INTR(port));  in mvebu_uart_stop_rx()
225 	ctl = readl(port->membase + UART_CTRL(port));  in mvebu_uart_break_ctl()
230 	writel(ctl, port->membase + UART_CTRL(port));  in mvebu_uart_break_ctl()
242 			ch = readl(port->membase + UART_RBR(port));  in mvebu_uart_rx_chars()
290 		status = readl(port->membase + UART_STAT);  in mvebu_uart_rx_chars()
303 		writel(port->x_char, port->membase + UART_TSH(port));  in mvebu_uart_tx_chars()
315 		writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));  in mvebu_uart_tx_chars()
322 		st = readl(port->membase + UART_STAT);  in mvebu_uart_tx_chars()
337 	unsigned int st = readl(port->membase + UART_STAT);  in mvebu_uart_isr()
352 	unsigned int st = readl(port->membase + UART_STAT);  in mvebu_uart_rx_isr()
364 	unsigned int st = readl(port->membase + UART_STAT);  in mvebu_uart_tx_isr()
379 	       port->membase + UART_CTRL(port));  in mvebu_uart_startup()
383 	ret = readl(port->membase + UART_STAT);  in mvebu_uart_startup()
385 	writel(ret, port->membase + UART_STAT);  in mvebu_uart_startup()
387 	writel(CTRL_BRK_INT, port->membase + UART_CTRL(port));  in mvebu_uart_startup()
389 	ctl = readl(port->membase + UART_INTR(port));  in mvebu_uart_startup()
391 	writel(ctl, port->membase + UART_INTR(port));  in mvebu_uart_startup()
434 	writel(0, port->membase + UART_INTR(port));  in mvebu_uart_shutdown()
461 	brdv = readl(port->membase + UART_BRDV);  in mvebu_uart_baud_rate_set()
464 	writel(brdv, port->membase + UART_BRDV);  in mvebu_uart_baud_rate_set()
538 	unsigned int st = readl(port->membase + UART_STAT);  in mvebu_uart_get_poll_char()
543 	return readl(port->membase + UART_RBR(port));  in mvebu_uart_get_poll_char()
551 		st = readl(port->membase + UART_STAT);  in mvebu_uart_put_poll_char()
559 	writel(c, port->membase + UART_TSH(port));  in mvebu_uart_put_poll_char()
592 		st = readl(port->membase + UART_STAT);  in mvebu_uart_putc()
598 	writel(c, port->membase + UART_STD_TSH);  in mvebu_uart_putc()
601 		st = readl(port->membase + UART_STAT);  in mvebu_uart_putc()
620 	if (!device->port.membase)  in mvebu_uart_early_console_setup()
636 	readl_poll_timeout_atomic(port->membase + UART_STAT, val,  in wait_for_xmitr()
643 	writel(ch, port->membase + UART_TSH(port));  in mvebu_uart_console_putchar()
659 	ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT;  in mvebu_uart_console_write()
660 	intr = readl(port->membase + UART_INTR(port)) &  in mvebu_uart_console_write()
662 	writel(0, port->membase + UART_CTRL(port));  in mvebu_uart_console_write()
663 	writel(0, port->membase + UART_INTR(port));  in mvebu_uart_console_write()
670 		writel(ier, port->membase + UART_CTRL(port));  in mvebu_uart_console_write()
673 		ctl = intr | readl(port->membase + UART_INTR(port));  in mvebu_uart_console_write()
674 		writel(ctl, port->membase + UART_INTR(port));  in mvebu_uart_console_write()
694 	if (!port->mapbase || !port->membase) {  in mvebu_uart_console_setup()
746 	mvuart->pm_regs.rbr = readl(port->membase + UART_RBR(port));  in mvebu_uart_suspend()
747 	mvuart->pm_regs.tsh = readl(port->membase + UART_TSH(port));  in mvebu_uart_suspend()
748 	mvuart->pm_regs.ctrl = readl(port->membase + UART_CTRL(port));  in mvebu_uart_suspend()
749 	mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port));  in mvebu_uart_suspend()
750 	mvuart->pm_regs.stat = readl(port->membase + UART_STAT);  in mvebu_uart_suspend()
751 	mvuart->pm_regs.brdv = readl(port->membase + UART_BRDV);  in mvebu_uart_suspend()
752 	mvuart->pm_regs.osamp = readl(port->membase + UART_OSAMP);  in mvebu_uart_suspend()
764 	writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port));  in mvebu_uart_resume()
765 	writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port));  in mvebu_uart_resume()
766 	writel(mvuart->pm_regs.ctrl, port->membase + UART_CTRL(port));  in mvebu_uart_resume()
767 	writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port));  in mvebu_uart_resume()
768 	writel(mvuart->pm_regs.stat, port->membase + UART_STAT);  in mvebu_uart_resume()
769 	writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV);  in mvebu_uart_resume()
770 	writel(mvuart->pm_regs.osamp, port->membase + UART_OSAMP);  in mvebu_uart_resume()
838 	port->membase = devm_ioremap_resource(&pdev->dev, reg);  in mvebu_uart_probe()
839 	if (IS_ERR(port->membase))  in mvebu_uart_probe()
840 		return -PTR_ERR(port->membase);  in mvebu_uart_probe()
903 	writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port));  in mvebu_uart_probe()
905 	writel(0, port->membase + UART_CTRL(port));  in mvebu_uart_probe()