109 	val = readl(port->membase + UART_CR);  in netx_stop_tx()
110 	writel(val & ~CR_TIE,  port->membase + UART_CR);  in netx_stop_tx()
116 	val = readl(port->membase + UART_CR);  in netx_stop_rx()
117 	writel(val & ~CR_RIE,  port->membase + UART_CR);  in netx_stop_rx()
123 	val = readl(port->membase + UART_CR);  in netx_enable_ms()
124 	writel(val | CR_MSIE, port->membase + UART_CR);  in netx_enable_ms()
132 		writel(port->x_char, port->membase + UART_DR);  in netx_transmit_buffer()
146 		writel(xmit->buf[xmit->tail], port->membase + UART_DR);  in netx_transmit_buffer()
152 	} while (!(readl(port->membase + UART_FR) & FR_TXFF));  in netx_transmit_buffer()
161 	    readl(port->membase + UART_CR) | CR_TIE, port->membase + UART_CR);  in netx_start_tx()
163 	if (!(readl(port->membase + UART_FR) & FR_TXFF))  in netx_start_tx()
169 	return readl(port->membase + UART_FR) & FR_BUSY ? 0 : TIOCSER_TEMT;  in netx_tx_empty()
191 	while (!(readl(port->membase + UART_FR) & FR_RXFE)) {  in netx_rxint()
192 		rx = readl(port->membase + UART_DR);  in netx_rxint()
195 		status = readl(port->membase + UART_SR);  in netx_rxint()
197 			writel(0, port->membase + UART_SR);  in netx_rxint()
240 	status = readl(port->membase + UART_IIR) & IIR_MASK;  in netx_int()
247 			if (readl(port->membase + UART_FR) & FR_CTS)  in netx_int()
252 		writel(0, port->membase + UART_IIR);  in netx_int()
253 		status = readl(port->membase + UART_IIR) & IIR_MASK;  in netx_int()
264 	if (readl(port->membase + UART_FR) & FR_CTS)  in netx_get_mctrl()
276 		val = readl(port->membase + UART_RTS_CR);  in netx_set_mctrl()
277 		writel(val | RTS_CR_RTS, port->membase + UART_RTS_CR);  in netx_set_mctrl()
286 	line_cr = readl(port->membase + UART_LINE_CR);  in netx_break_ctl()
291 	writel(line_cr, port->membase + UART_LINE_CR);  in netx_break_ctl()
307 	writel(readl(port->membase + UART_LINE_CR) | LINE_CR_FEN,  in netx_startup()
308 		port->membase + UART_LINE_CR);  in netx_startup()
311 		port->membase + UART_CR);  in netx_startup()
319 	writel(0, port->membase + UART_CR) ;  in netx_shutdown()
370 	old_cr = readl(port->membase + UART_CR);  in netx_set_termios()
374 		port->membase + UART_CR);  in netx_set_termios()
377 	while (readl(port->membase + UART_FR) & FR_BUSY);  in netx_set_termios()
380 	writel(old_cr & ~CR_UART_EN, port->membase + UART_CR);  in netx_set_termios()
387 	writel((quot>>8) & 0xff, port->membase + UART_BAUDDIV_MSB);  in netx_set_termios()
388 	writel(quot & 0xff, port->membase + UART_BAUDDIV_LSB);  in netx_set_termios()
389 	writel(line_cr, port->membase + UART_LINE_CR);  in netx_set_termios()
391 	writel(rts_cr, port->membase + UART_RTS_CR);  in netx_set_termios()
415 	writel(old_cr, port->membase + UART_CR);  in netx_set_termios()
477 		.membase = (char __iomem *)io_p2v(NETX_PA_UART0),
490 		.membase = (char __iomem *)io_p2v(NETX_PA_UART1),
503 		.membase = (char __iomem *)io_p2v(NETX_PA_UART2),
519 	while (readl(port->membase + UART_FR) & FR_BUSY);  in netx_console_putchar()
520 	writel(ch, port->membase + UART_DR);  in netx_console_putchar()
529 	cr_save = readl(port->membase + UART_CR);  in netx_console_write()
530 	writel(cr_save | CR_UART_EN, port->membase + UART_CR);  in netx_console_write()
534 	while (readl(port->membase + UART_FR) & FR_BUSY);  in netx_console_write()
535 	writel(cr_save, port->membase + UART_CR);  in netx_console_write()
544 	*baud = (readl(port->membase + UART_BAUDDIV_MSB) << 8) |  in netx_console_get_options()
545 		readl(port->membase + UART_BAUDDIV_LSB);  in netx_console_get_options()
552 	line_cr = readl(port->membase + UART_LINE_CR);  in netx_console_get_options()
576 	if (readl(port->membase + UART_RTS_CR) & RTS_CR_AUTO)  in netx_console_get_options()
604 		if (readl(sport->port.membase + UART_CR) & CR_UART_EN) {  in netx_console_setup()
675 	writel(1, port->membase + UART_RXFIFO_IRQLEVEL);  in serial_netx_probe()