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Searched refs:clk_set_parent (Results 1 – 25 of 98) sorted by relevance

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/Linux-v4.19/drivers/clk/imx/
Dclk-imx6sx.c181 clk_set_parent(clks[IMX6SX_PLL1_BYPASS], clks[IMX6SX_CLK_PLL1]); in imx6sx_clocks_init()
182 clk_set_parent(clks[IMX6SX_PLL2_BYPASS], clks[IMX6SX_CLK_PLL2]); in imx6sx_clocks_init()
183 clk_set_parent(clks[IMX6SX_PLL3_BYPASS], clks[IMX6SX_CLK_PLL3]); in imx6sx_clocks_init()
184 clk_set_parent(clks[IMX6SX_PLL4_BYPASS], clks[IMX6SX_CLK_PLL4]); in imx6sx_clocks_init()
185 clk_set_parent(clks[IMX6SX_PLL5_BYPASS], clks[IMX6SX_CLK_PLL5]); in imx6sx_clocks_init()
186 clk_set_parent(clks[IMX6SX_PLL6_BYPASS], clks[IMX6SX_CLK_PLL6]); in imx6sx_clocks_init()
187 clk_set_parent(clks[IMX6SX_PLL7_BYPASS], clks[IMX6SX_CLK_PLL7]); in imx6sx_clocks_init()
503 clk_set_parent(clks[IMX6SX_CLK_EIM_SLOW_SEL], clks[IMX6SX_CLK_PLL2_PFD2]); in imx6sx_clocks_init()
507 clk_set_parent(clks[IMX6SX_CLK_LCDIF1_PRE_SEL], clks[IMX6SX_CLK_PLL5_VIDEO_DIV]); in imx6sx_clocks_init()
508 clk_set_parent(clks[IMX6SX_CLK_LCDIF1_SEL], clks[IMX6SX_CLK_LCDIF1_PODF]); in imx6sx_clocks_init()
[all …]
Dclk-imx6q.c256 clk_set_parent(clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL], in mmdc_ch1_disable()
263 clk_set_parent(clk[IMX6QDL_CLK_PERIPH2], clk[IMX6QDL_CLK_PERIPH2_CLK2]); in mmdc_ch1_disable()
280 clk_set_parent(clk[IMX6QDL_CLK_PERIPH2], clk[IMX6QDL_CLK_PERIPH2_PRE]); in mmdc_ch1_reenable()
462 clk_set_parent(clk[IMX6QDL_PLL1_BYPASS], clk[IMX6QDL_CLK_PLL1]); in imx6q_clocks_init()
463 clk_set_parent(clk[IMX6QDL_PLL2_BYPASS], clk[IMX6QDL_CLK_PLL2]); in imx6q_clocks_init()
464 clk_set_parent(clk[IMX6QDL_PLL3_BYPASS], clk[IMX6QDL_CLK_PLL3]); in imx6q_clocks_init()
465 clk_set_parent(clk[IMX6QDL_PLL4_BYPASS], clk[IMX6QDL_CLK_PLL4]); in imx6q_clocks_init()
466 clk_set_parent(clk[IMX6QDL_PLL5_BYPASS], clk[IMX6QDL_CLK_PLL5]); in imx6q_clocks_init()
467 clk_set_parent(clk[IMX6QDL_PLL6_BYPASS], clk[IMX6QDL_CLK_PLL6]); in imx6q_clocks_init()
468 clk_set_parent(clk[IMX6QDL_PLL7_BYPASS], clk[IMX6QDL_CLK_PLL7]); in imx6q_clocks_init()
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Dclk-imx6ul.c167 clk_set_parent(clks[IMX6UL_PLL1_BYPASS], clks[IMX6UL_CLK_PLL1]); in imx6ul_clocks_init()
168 clk_set_parent(clks[IMX6UL_PLL2_BYPASS], clks[IMX6UL_CLK_PLL2]); in imx6ul_clocks_init()
169 clk_set_parent(clks[IMX6UL_PLL3_BYPASS], clks[IMX6UL_CLK_PLL3]); in imx6ul_clocks_init()
170 clk_set_parent(clks[IMX6UL_PLL4_BYPASS], clks[IMX6UL_CLK_PLL4]); in imx6ul_clocks_init()
171 clk_set_parent(clks[IMX6UL_PLL5_BYPASS], clks[IMX6UL_CLK_PLL5]); in imx6ul_clocks_init()
172 clk_set_parent(clks[IMX6UL_PLL6_BYPASS], clks[IMX6UL_CLK_PLL6]); in imx6ul_clocks_init()
173 clk_set_parent(clks[IMX6UL_PLL7_BYPASS], clks[IMX6UL_CLK_PLL7]); in imx6ul_clocks_init()
484 clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL], clks[IMX6UL_CLK_OSC]); in imx6ul_clocks_init()
485 clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_CLK2]); in imx6ul_clocks_init()
486 clk_set_parent(clks[IMX6UL_CLK_PERIPH_PRE], clks[IMX6UL_CLK_PLL2_BUS]); in imx6ul_clocks_init()
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Dclk-vf610.c239 clk_set_parent(clk[VF610_PLL1_BYPASS], clk[VF610_CLK_PLL1]); in vf610_clocks_init()
240 clk_set_parent(clk[VF610_PLL2_BYPASS], clk[VF610_CLK_PLL2]); in vf610_clocks_init()
241 clk_set_parent(clk[VF610_PLL3_BYPASS], clk[VF610_CLK_PLL3]); in vf610_clocks_init()
242 clk_set_parent(clk[VF610_PLL4_BYPASS], clk[VF610_CLK_PLL4]); in vf610_clocks_init()
243 clk_set_parent(clk[VF610_PLL5_BYPASS], clk[VF610_CLK_PLL5]); in vf610_clocks_init()
244 clk_set_parent(clk[VF610_PLL6_BYPASS], clk[VF610_CLK_PLL6]); in vf610_clocks_init()
245 clk_set_parent(clk[VF610_PLL7_BYPASS], clk[VF610_CLK_PLL7]); in vf610_clocks_init()
448 clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]); in vf610_clocks_init()
453 clk_set_parent(clk[VF610_CLK_QSPI1_SEL], clk[VF610_CLK_PLL1_PFD4]); in vf610_clocks_init()
458 clk_set_parent(clk[VF610_CLK_SAI0_SEL], clk[VF610_CLK_AUDIO_EXT]); in vf610_clocks_init()
[all …]
Dclk-cpu.c53 ret = clk_set_parent(cpu->mux, cpu->step); in clk_cpu_set_rate()
60 clk_set_parent(cpu->mux, cpu->pll); in clk_cpu_set_rate()
64 clk_set_parent(cpu->mux, cpu->pll); in clk_cpu_set_rate()
Dclk-imx6sl.c233 clk_set_parent(clks[IMX6SL_PLL1_BYPASS], clks[IMX6SL_CLK_PLL1]); in imx6sl_clocks_init()
234 clk_set_parent(clks[IMX6SL_PLL2_BYPASS], clks[IMX6SL_CLK_PLL2]); in imx6sl_clocks_init()
235 clk_set_parent(clks[IMX6SL_PLL3_BYPASS], clks[IMX6SL_CLK_PLL3]); in imx6sl_clocks_init()
236 clk_set_parent(clks[IMX6SL_PLL4_BYPASS], clks[IMX6SL_CLK_PLL4]); in imx6sl_clocks_init()
237 clk_set_parent(clks[IMX6SL_PLL5_BYPASS], clks[IMX6SL_CLK_PLL5]); in imx6sl_clocks_init()
238 clk_set_parent(clks[IMX6SL_PLL6_BYPASS], clks[IMX6SL_CLK_PLL6]); in imx6sl_clocks_init()
239 clk_set_parent(clks[IMX6SL_PLL7_BYPASS], clks[IMX6SL_CLK_PLL7]); in imx6sl_clocks_init()
430 clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]); in imx6sl_clocks_init()
433 clk_set_parent(clks[IMX6SL_CLK_LCDIF_PIX_SEL], in imx6sl_clocks_init()
436 clk_set_parent(clks[IMX6SL_CLK_LCDIF_AXI_SEL], in imx6sl_clocks_init()
Dclk-imx7d.c889 clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]); in imx7d_clocks_init()
890 clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]); in imx7d_clocks_init()
891 clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]); in imx7d_clocks_init()
892 clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MAIN]); in imx7d_clocks_init()
893 clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]); in imx7d_clocks_init()
894 clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]); in imx7d_clocks_init()
896 clk_set_parent(clks[IMX7D_MIPI_CSI_ROOT_SRC], clks[IMX7D_PLL_SYS_PFD3_CLK]); in imx7d_clocks_init()
899 clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]); in imx7d_clocks_init()
902 clk_set_parent(clks[IMX7D_UART1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]); in imx7d_clocks_init()
Dclk-imx51-imx53.c315 clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]); in mx5_clocks_common_init()
316 clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]); in mx5_clocks_common_init()
319 clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]); in mx5_clocks_common_init()
452 clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]); in mx51_clocks_init()
596 clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]); in mx53_clocks_init()
599 clk_set_parent(clk[IMX5_CLK_STEP_SEL], clk[IMX5_CLK_LP_APM]); in mx53_clocks_init()
/Linux-v4.19/drivers/cpufreq/
Dtegra124-cpufreq.c47 clk_set_parent(priv->cpu_clk, priv->pllp_clk); in tegra124_cpu_switch_to_dfll()
53 clk_set_parent(priv->cpu_clk, priv->dfll_clk); in tegra124_cpu_switch_to_dfll()
58 clk_set_parent(priv->cpu_clk, orig_parent); in tegra124_cpu_switch_to_dfll()
65 clk_set_parent(priv->cpu_clk, priv->pllp_clk); in tegra124_cpu_switch_to_pllx()
68 clk_set_parent(priv->cpu_clk, priv->pllx_clk); in tegra124_cpu_switch_to_pllx()
Dimx6q-cpufreq.c133 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); in imx6q_set_target()
135 clk_set_parent(clks[SECONDARY_SEL].clk, in imx6q_set_target()
138 clk_set_parent(clks[SECONDARY_SEL].clk, in imx6q_set_target()
140 clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk); in imx6q_set_target()
141 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk); in imx6q_set_target()
144 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); in imx6q_set_target()
147 clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk); in imx6q_set_target()
148 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk); in imx6q_set_target()
151 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); in imx6q_set_target()
Dtegra20-cpufreq.c83 ret = clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_p_clk); in tegra_target_intermediate()
104 return clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_p_clk); in tegra_target()
111 ret = clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_x_clk); in tegra_target()
Dmediatek-cpufreq.c260 ret = clk_set_parent(cpu_clk, info->inter_clk); in mtk_cpufreq_set_target()
274 clk_set_parent(cpu_clk, armpll); in mtk_cpufreq_set_target()
280 ret = clk_set_parent(cpu_clk, armpll); in mtk_cpufreq_set_target()
298 clk_set_parent(cpu_clk, info->inter_clk); in mtk_cpufreq_set_target()
300 clk_set_parent(cpu_clk, armpll); in mtk_cpufreq_set_target()
Dkirkwood-cpufreq.c69 clk_set_parent(priv.powersave_clk, priv.cpu_clk); in kirkwood_cpufreq_target()
72 clk_set_parent(priv.powersave_clk, priv.ddr_clk); in kirkwood_cpufreq_target()
Dloongson1-cpufreq.c66 clk_set_parent(policy->clk, cpufreq->osc_clk); in ls1x_cpufreq_target()
72 clk_set_parent(policy->clk, cpufreq->mux_clk); in ls1x_cpufreq_target()
/Linux-v4.19/sound/soc/samsung/
Dsmdk_spdif.c61 clk_set_parent(mout_epll, fout_epll); in set_audio_clock_heirachy()
62 clk_set_parent(sclk_audio0, mout_epll); in set_audio_clock_heirachy()
63 clk_set_parent(sclk_spdif, sclk_audio0); in set_audio_clock_heirachy()
/Linux-v4.19/arch/arm/mach-w90x900/
Dclock.c112 int clk_set_parent(struct clk *clk, struct clk *parent) in clk_set_parent() function
117 EXPORT_SYMBOL(clk_set_parent);
/Linux-v4.19/drivers/media/platform/mtk-vcodec/
Dmtk_vcodec_dec_pm.c155 ret = clk_set_parent(pm->venc_lt_sel, pm->vdec_bus_clk_src); in mtk_vcodec_dec_clock_on()
168 ret = clk_set_parent(pm->clk_cci400_sel, pm->univpll_d2); in mtk_vcodec_dec_clock_on()
181 ret = clk_set_parent(pm->vdec_sel, pm->vdecpll); in mtk_vcodec_dec_clock_on()
Dmtk_vcodec_enc_pm.c109 ret = clk_set_parent(pm->venc_sel, pm->vencpll_d2); in mtk_vcodec_enc_clock_on()
117 ret = clk_set_parent(pm->venc_lt_sel, pm->univpll1_d2); in mtk_vcodec_enc_clock_on()
/Linux-v4.19/drivers/clk/ti/
Dclk-33xx.c255 clk_set_parent(clk2, clk1); in am33xx_dt_clk_init()
258 clk_set_parent(clk2, clk1); in am33xx_dt_clk_init()
268 clk_set_parent(clk1, clk2); in am33xx_dt_clk_init()
/Linux-v4.19/arch/arm/mach-sa1100/
Dclock.c52 int clk_set_parent(struct clk *clk, struct clk *parent) in clk_set_parent() function
56 EXPORT_SYMBOL(clk_set_parent);
/Linux-v4.19/arch/m68k/coldfire/
Dclk.c147 int clk_set_parent(struct clk *clk, struct clk *parent) in clk_set_parent() function
152 EXPORT_SYMBOL(clk_set_parent);
/Linux-v4.19/drivers/clk/mmp/
Dclk-pxa910.c208 clk_set_parent(clk, uart_pll); in pxa910_clk_init()
219 clk_set_parent(clk, uart_pll); in pxa910_clk_init()
230 clk_set_parent(clk, uart_pll); in pxa910_clk_init()
Dclk-mmp2.c249 clk_set_parent(clk, vctcxo); in mmp2_clk_init()
260 clk_set_parent(clk, vctcxo); in mmp2_clk_init()
271 clk_set_parent(clk, vctcxo); in mmp2_clk_init()
282 clk_set_parent(clk, vctcxo); in mmp2_clk_init()
Dclk-pxa168.c203 clk_set_parent(clk, uart_pll); in pxa168_clk_init()
214 clk_set_parent(clk, uart_pll); in pxa168_clk_init()
225 clk_set_parent(clk, uart_pll); in pxa168_clk_init()
/Linux-v4.19/drivers/gpu/drm/imx/
Dimx-ldb.c195 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]); in imx_ldb_set_clock()
212 clk_set_parent(ldb->clk_sel[mux], ldb->clk[0]); in imx_ldb_encoder_enable()
213 clk_set_parent(ldb->clk_sel[mux], ldb->clk[1]); in imx_ldb_encoder_enable()
218 clk_set_parent(ldb->clk_sel[mux], ldb->clk[imx_ldb_ch->chno]); in imx_ldb_encoder_enable()
346 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]); in imx_ldb_encoder_disable()

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