1 /*
2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/cpu.h>
11 #include <linux/cpufreq.h>
12 #include <linux/cpu_cooling.h>
13 #include <linux/err.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/pm_opp.h>
18 #include <linux/platform_device.h>
19 #include <linux/regulator/consumer.h>
20
21 #define PU_SOC_VOLTAGE_NORMAL 1250000
22 #define PU_SOC_VOLTAGE_HIGH 1275000
23 #define FREQ_1P2_GHZ 1200000000
24
25 static struct regulator *arm_reg;
26 static struct regulator *pu_reg;
27 static struct regulator *soc_reg;
28
29 enum IMX6_CPUFREQ_CLKS {
30 ARM,
31 PLL1_SYS,
32 STEP,
33 PLL1_SW,
34 PLL2_PFD2_396M,
35 /* MX6UL requires two more clks */
36 PLL2_BUS,
37 SECONDARY_SEL,
38 };
39 #define IMX6Q_CPUFREQ_CLK_NUM 5
40 #define IMX6UL_CPUFREQ_CLK_NUM 7
41
42 static int num_clks;
43 static struct clk_bulk_data clks[] = {
44 { .id = "arm" },
45 { .id = "pll1_sys" },
46 { .id = "step" },
47 { .id = "pll1_sw" },
48 { .id = "pll2_pfd2_396m" },
49 { .id = "pll2_bus" },
50 { .id = "secondary_sel" },
51 };
52
53 static struct device *cpu_dev;
54 static struct thermal_cooling_device *cdev;
55 static bool free_opp;
56 static struct cpufreq_frequency_table *freq_table;
57 static unsigned int max_freq;
58 static unsigned int transition_latency;
59
60 static u32 *imx6_soc_volt;
61 static u32 soc_opp_count;
62
imx6q_set_target(struct cpufreq_policy * policy,unsigned int index)63 static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
64 {
65 struct dev_pm_opp *opp;
66 unsigned long freq_hz, volt, volt_old;
67 unsigned int old_freq, new_freq;
68 bool pll1_sys_temp_enabled = false;
69 int ret;
70
71 new_freq = freq_table[index].frequency;
72 freq_hz = new_freq * 1000;
73 old_freq = clk_get_rate(clks[ARM].clk) / 1000;
74
75 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
76 if (IS_ERR(opp)) {
77 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
78 return PTR_ERR(opp);
79 }
80
81 volt = dev_pm_opp_get_voltage(opp);
82 dev_pm_opp_put(opp);
83
84 volt_old = regulator_get_voltage(arm_reg);
85
86 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
87 old_freq / 1000, volt_old / 1000,
88 new_freq / 1000, volt / 1000);
89
90 /* scaling up? scale voltage before frequency */
91 if (new_freq > old_freq) {
92 if (!IS_ERR(pu_reg)) {
93 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
94 if (ret) {
95 dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
96 return ret;
97 }
98 }
99 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
100 if (ret) {
101 dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
102 return ret;
103 }
104 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
105 if (ret) {
106 dev_err(cpu_dev,
107 "failed to scale vddarm up: %d\n", ret);
108 return ret;
109 }
110 }
111
112 /*
113 * The setpoints are selected per PLL/PDF frequencies, so we need to
114 * reprogram PLL for frequency scaling. The procedure of reprogramming
115 * PLL1 is as below.
116 * For i.MX6UL, it has a secondary clk mux, the cpu frequency change
117 * flow is slightly different from other i.MX6 OSC.
118 * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below:
119 * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
120 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
121 * - Disable pll2_pfd2_396m_clk
122 */
123 if (of_machine_is_compatible("fsl,imx6ul") ||
124 of_machine_is_compatible("fsl,imx6ull")) {
125 /*
126 * When changing pll1_sw_clk's parent to pll1_sys_clk,
127 * CPU may run at higher than 528MHz, this will lead to
128 * the system unstable if the voltage is lower than the
129 * voltage of 528MHz, so lower the CPU frequency to one
130 * half before changing CPU frequency.
131 */
132 clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000);
133 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
134 if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk))
135 clk_set_parent(clks[SECONDARY_SEL].clk,
136 clks[PLL2_BUS].clk);
137 else
138 clk_set_parent(clks[SECONDARY_SEL].clk,
139 clks[PLL2_PFD2_396M].clk);
140 clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk);
141 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
142 if (freq_hz > clk_get_rate(clks[PLL2_BUS].clk)) {
143 clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
144 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
145 }
146 } else {
147 clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk);
148 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
149 if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) {
150 clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
151 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
152 } else {
153 /* pll1_sys needs to be enabled for divider rate change to work. */
154 pll1_sys_temp_enabled = true;
155 clk_prepare_enable(clks[PLL1_SYS].clk);
156 }
157 }
158
159 /* Ensure the arm clock divider is what we expect */
160 ret = clk_set_rate(clks[ARM].clk, new_freq * 1000);
161 if (ret) {
162 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
163 regulator_set_voltage_tol(arm_reg, volt_old, 0);
164 return ret;
165 }
166
167 /* PLL1 is only needed until after ARM-PODF is set. */
168 if (pll1_sys_temp_enabled)
169 clk_disable_unprepare(clks[PLL1_SYS].clk);
170
171 /* scaling down? scale voltage after frequency */
172 if (new_freq < old_freq) {
173 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
174 if (ret) {
175 dev_warn(cpu_dev,
176 "failed to scale vddarm down: %d\n", ret);
177 ret = 0;
178 }
179 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
180 if (ret) {
181 dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
182 ret = 0;
183 }
184 if (!IS_ERR(pu_reg)) {
185 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
186 if (ret) {
187 dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
188 ret = 0;
189 }
190 }
191 }
192
193 return 0;
194 }
195
imx6q_cpufreq_ready(struct cpufreq_policy * policy)196 static void imx6q_cpufreq_ready(struct cpufreq_policy *policy)
197 {
198 cdev = of_cpufreq_cooling_register(policy);
199
200 if (!cdev)
201 dev_err(cpu_dev,
202 "running cpufreq without cooling device: %ld\n",
203 PTR_ERR(cdev));
204 }
205
imx6q_cpufreq_init(struct cpufreq_policy * policy)206 static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
207 {
208 int ret;
209
210 policy->clk = clks[ARM].clk;
211 ret = cpufreq_generic_init(policy, freq_table, transition_latency);
212 policy->suspend_freq = max_freq;
213
214 return ret;
215 }
216
imx6q_cpufreq_exit(struct cpufreq_policy * policy)217 static int imx6q_cpufreq_exit(struct cpufreq_policy *policy)
218 {
219 cpufreq_cooling_unregister(cdev);
220
221 return 0;
222 }
223
224 static struct cpufreq_driver imx6q_cpufreq_driver = {
225 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
226 .verify = cpufreq_generic_frequency_table_verify,
227 .target_index = imx6q_set_target,
228 .get = cpufreq_generic_get,
229 .init = imx6q_cpufreq_init,
230 .exit = imx6q_cpufreq_exit,
231 .name = "imx6q-cpufreq",
232 .ready = imx6q_cpufreq_ready,
233 .attr = cpufreq_generic_attr,
234 .suspend = cpufreq_generic_suspend,
235 };
236
237 #define OCOTP_CFG3 0x440
238 #define OCOTP_CFG3_SPEED_SHIFT 16
239 #define OCOTP_CFG3_SPEED_1P2GHZ 0x3
240 #define OCOTP_CFG3_SPEED_996MHZ 0x2
241 #define OCOTP_CFG3_SPEED_852MHZ 0x1
242
imx6q_opp_check_speed_grading(struct device * dev)243 static void imx6q_opp_check_speed_grading(struct device *dev)
244 {
245 struct device_node *np;
246 void __iomem *base;
247 u32 val;
248
249 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
250 if (!np)
251 return;
252
253 base = of_iomap(np, 0);
254 if (!base) {
255 dev_err(dev, "failed to map ocotp\n");
256 goto put_node;
257 }
258
259 /*
260 * SPEED_GRADING[1:0] defines the max speed of ARM:
261 * 2b'11: 1200000000Hz;
262 * 2b'10: 996000000Hz;
263 * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
264 * 2b'00: 792000000Hz;
265 * We need to set the max speed of ARM according to fuse map.
266 */
267 val = readl_relaxed(base + OCOTP_CFG3);
268 val >>= OCOTP_CFG3_SPEED_SHIFT;
269 val &= 0x3;
270
271 if (val < OCOTP_CFG3_SPEED_996MHZ)
272 if (dev_pm_opp_disable(dev, 996000000))
273 dev_warn(dev, "failed to disable 996MHz OPP\n");
274
275 if (of_machine_is_compatible("fsl,imx6q") ||
276 of_machine_is_compatible("fsl,imx6qp")) {
277 if (val != OCOTP_CFG3_SPEED_852MHZ)
278 if (dev_pm_opp_disable(dev, 852000000))
279 dev_warn(dev, "failed to disable 852MHz OPP\n");
280 if (val != OCOTP_CFG3_SPEED_1P2GHZ)
281 if (dev_pm_opp_disable(dev, 1200000000))
282 dev_warn(dev, "failed to disable 1.2GHz OPP\n");
283 }
284 iounmap(base);
285 put_node:
286 of_node_put(np);
287 }
288
289 #define OCOTP_CFG3_6UL_SPEED_696MHZ 0x2
290 #define OCOTP_CFG3_6ULL_SPEED_792MHZ 0x2
291 #define OCOTP_CFG3_6ULL_SPEED_900MHZ 0x3
292
imx6ul_opp_check_speed_grading(struct device * dev)293 static void imx6ul_opp_check_speed_grading(struct device *dev)
294 {
295 struct device_node *np;
296 void __iomem *base;
297 u32 val;
298
299 np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
300 if (!np)
301 return;
302
303 base = of_iomap(np, 0);
304 if (!base) {
305 dev_err(dev, "failed to map ocotp\n");
306 goto put_node;
307 }
308
309 /*
310 * Speed GRADING[1:0] defines the max speed of ARM:
311 * 2b'00: Reserved;
312 * 2b'01: 528000000Hz;
313 * 2b'10: 696000000Hz on i.MX6UL, 792000000Hz on i.MX6ULL;
314 * 2b'11: 900000000Hz on i.MX6ULL only;
315 * We need to set the max speed of ARM according to fuse map.
316 */
317 val = readl_relaxed(base + OCOTP_CFG3);
318 val >>= OCOTP_CFG3_SPEED_SHIFT;
319 val &= 0x3;
320
321 if (of_machine_is_compatible("fsl,imx6ul")) {
322 if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
323 if (dev_pm_opp_disable(dev, 696000000))
324 dev_warn(dev, "failed to disable 696MHz OPP\n");
325 }
326
327 if (of_machine_is_compatible("fsl,imx6ull")) {
328 if (val != OCOTP_CFG3_6ULL_SPEED_792MHZ)
329 if (dev_pm_opp_disable(dev, 792000000))
330 dev_warn(dev, "failed to disable 792MHz OPP\n");
331
332 if (val != OCOTP_CFG3_6ULL_SPEED_900MHZ)
333 if (dev_pm_opp_disable(dev, 900000000))
334 dev_warn(dev, "failed to disable 900MHz OPP\n");
335 }
336
337 iounmap(base);
338 put_node:
339 of_node_put(np);
340 }
341
imx6q_cpufreq_probe(struct platform_device * pdev)342 static int imx6q_cpufreq_probe(struct platform_device *pdev)
343 {
344 struct device_node *np;
345 struct dev_pm_opp *opp;
346 unsigned long min_volt, max_volt;
347 int num, ret;
348 const struct property *prop;
349 const __be32 *val;
350 u32 nr, i, j;
351
352 cpu_dev = get_cpu_device(0);
353 if (!cpu_dev) {
354 pr_err("failed to get cpu0 device\n");
355 return -ENODEV;
356 }
357
358 np = of_node_get(cpu_dev->of_node);
359 if (!np) {
360 dev_err(cpu_dev, "failed to find cpu0 node\n");
361 return -ENOENT;
362 }
363
364 if (of_machine_is_compatible("fsl,imx6ul") ||
365 of_machine_is_compatible("fsl,imx6ull"))
366 num_clks = IMX6UL_CPUFREQ_CLK_NUM;
367 else
368 num_clks = IMX6Q_CPUFREQ_CLK_NUM;
369
370 ret = clk_bulk_get(cpu_dev, num_clks, clks);
371 if (ret)
372 goto put_node;
373
374 arm_reg = regulator_get(cpu_dev, "arm");
375 pu_reg = regulator_get_optional(cpu_dev, "pu");
376 soc_reg = regulator_get(cpu_dev, "soc");
377 if (PTR_ERR(arm_reg) == -EPROBE_DEFER ||
378 PTR_ERR(soc_reg) == -EPROBE_DEFER ||
379 PTR_ERR(pu_reg) == -EPROBE_DEFER) {
380 ret = -EPROBE_DEFER;
381 dev_dbg(cpu_dev, "regulators not ready, defer\n");
382 goto put_reg;
383 }
384 if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) {
385 dev_err(cpu_dev, "failed to get regulators\n");
386 ret = -ENOENT;
387 goto put_reg;
388 }
389
390 ret = dev_pm_opp_of_add_table(cpu_dev);
391 if (ret < 0) {
392 dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
393 goto put_reg;
394 }
395
396 if (of_machine_is_compatible("fsl,imx6ul") ||
397 of_machine_is_compatible("fsl,imx6ull"))
398 imx6ul_opp_check_speed_grading(cpu_dev);
399 else
400 imx6q_opp_check_speed_grading(cpu_dev);
401
402 /* Because we have added the OPPs here, we must free them */
403 free_opp = true;
404 num = dev_pm_opp_get_opp_count(cpu_dev);
405 if (num < 0) {
406 ret = num;
407 dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
408 goto out_free_opp;
409 }
410
411 ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
412 if (ret) {
413 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
414 goto out_free_opp;
415 }
416
417 /* Make imx6_soc_volt array's size same as arm opp number */
418 imx6_soc_volt = devm_kcalloc(cpu_dev, num, sizeof(*imx6_soc_volt),
419 GFP_KERNEL);
420 if (imx6_soc_volt == NULL) {
421 ret = -ENOMEM;
422 goto free_freq_table;
423 }
424
425 prop = of_find_property(np, "fsl,soc-operating-points", NULL);
426 if (!prop || !prop->value)
427 goto soc_opp_out;
428
429 /*
430 * Each OPP is a set of tuples consisting of frequency and
431 * voltage like <freq-kHz vol-uV>.
432 */
433 nr = prop->length / sizeof(u32);
434 if (nr % 2 || (nr / 2) < num)
435 goto soc_opp_out;
436
437 for (j = 0; j < num; j++) {
438 val = prop->value;
439 for (i = 0; i < nr / 2; i++) {
440 unsigned long freq = be32_to_cpup(val++);
441 unsigned long volt = be32_to_cpup(val++);
442 if (freq_table[j].frequency == freq) {
443 imx6_soc_volt[soc_opp_count++] = volt;
444 break;
445 }
446 }
447 }
448
449 soc_opp_out:
450 /* use fixed soc opp volt if no valid soc opp info found in dtb */
451 if (soc_opp_count != num) {
452 dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
453 for (j = 0; j < num; j++)
454 imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
455 if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
456 imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
457 }
458
459 if (of_property_read_u32(np, "clock-latency", &transition_latency))
460 transition_latency = CPUFREQ_ETERNAL;
461
462 /*
463 * Calculate the ramp time for max voltage change in the
464 * VDDSOC and VDDPU regulators.
465 */
466 ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
467 if (ret > 0)
468 transition_latency += ret * 1000;
469 if (!IS_ERR(pu_reg)) {
470 ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
471 if (ret > 0)
472 transition_latency += ret * 1000;
473 }
474
475 /*
476 * OPP is maintained in order of increasing frequency, and
477 * freq_table initialised from OPP is therefore sorted in the
478 * same order.
479 */
480 max_freq = freq_table[--num].frequency;
481 opp = dev_pm_opp_find_freq_exact(cpu_dev,
482 freq_table[0].frequency * 1000, true);
483 min_volt = dev_pm_opp_get_voltage(opp);
484 dev_pm_opp_put(opp);
485 opp = dev_pm_opp_find_freq_exact(cpu_dev, max_freq * 1000, true);
486 max_volt = dev_pm_opp_get_voltage(opp);
487 dev_pm_opp_put(opp);
488
489 ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
490 if (ret > 0)
491 transition_latency += ret * 1000;
492
493 ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
494 if (ret) {
495 dev_err(cpu_dev, "failed register driver: %d\n", ret);
496 goto free_freq_table;
497 }
498
499 of_node_put(np);
500 return 0;
501
502 free_freq_table:
503 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
504 out_free_opp:
505 if (free_opp)
506 dev_pm_opp_of_remove_table(cpu_dev);
507 put_reg:
508 if (!IS_ERR(arm_reg))
509 regulator_put(arm_reg);
510 if (!IS_ERR(pu_reg))
511 regulator_put(pu_reg);
512 if (!IS_ERR(soc_reg))
513 regulator_put(soc_reg);
514
515 clk_bulk_put(num_clks, clks);
516 put_node:
517 of_node_put(np);
518
519 return ret;
520 }
521
imx6q_cpufreq_remove(struct platform_device * pdev)522 static int imx6q_cpufreq_remove(struct platform_device *pdev)
523 {
524 cpufreq_unregister_driver(&imx6q_cpufreq_driver);
525 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
526 if (free_opp)
527 dev_pm_opp_of_remove_table(cpu_dev);
528 regulator_put(arm_reg);
529 if (!IS_ERR(pu_reg))
530 regulator_put(pu_reg);
531 regulator_put(soc_reg);
532
533 clk_bulk_put(num_clks, clks);
534
535 return 0;
536 }
537
538 static struct platform_driver imx6q_cpufreq_platdrv = {
539 .driver = {
540 .name = "imx6q-cpufreq",
541 },
542 .probe = imx6q_cpufreq_probe,
543 .remove = imx6q_cpufreq_remove,
544 };
545 module_platform_driver(imx6q_cpufreq_platdrv);
546
547 MODULE_ALIAS("platform:imx6q-cpufreq");
548 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
549 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
550 MODULE_LICENSE("GPL");
551
