1 /*
2 * pxa168 clock framework source file
3 *
4 * Copyright (C) 2012 Marvell
5 * Chao Xie <xiechao.mail@gmail.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/spinlock.h>
16 #include <linux/io.h>
17 #include <linux/delay.h>
18 #include <linux/err.h>
19
20 #include "clk.h"
21
22 #define APBC_RTC 0x28
23 #define APBC_TWSI0 0x2c
24 #define APBC_KPC 0x30
25 #define APBC_UART0 0x0
26 #define APBC_UART1 0x4
27 #define APBC_GPIO 0x8
28 #define APBC_PWM0 0xc
29 #define APBC_PWM1 0x10
30 #define APBC_PWM2 0x14
31 #define APBC_PWM3 0x18
32 #define APBC_SSP0 0x81c
33 #define APBC_SSP1 0x820
34 #define APBC_SSP2 0x84c
35 #define APBC_SSP3 0x858
36 #define APBC_SSP4 0x85c
37 #define APBC_TWSI1 0x6c
38 #define APBC_UART2 0x70
39 #define APMU_SDH0 0x54
40 #define APMU_SDH1 0x58
41 #define APMU_USB 0x5c
42 #define APMU_DISP0 0x4c
43 #define APMU_CCIC0 0x50
44 #define APMU_DFC 0x60
45 #define MPMU_UART_PLL 0x14
46
47 static DEFINE_SPINLOCK(clk_lock);
48
49 static struct mmp_clk_factor_masks uart_factor_masks = {
50 .factor = 2,
51 .num_mask = 0x1fff,
52 .den_mask = 0x1fff,
53 .num_shift = 16,
54 .den_shift = 0,
55 };
56
57 static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
58 {.num = 8125, .den = 1536}, /*14.745MHZ */
59 };
60
61 static const char *uart_parent[] = {"pll1_3_16", "uart_pll"};
62 static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
63 static const char *sdh_parent[] = {"pll1_12", "pll1_13"};
64 static const char *disp_parent[] = {"pll1_2", "pll1_12"};
65 static const char *ccic_parent[] = {"pll1_2", "pll1_12"};
66 static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"};
67
pxa168_clk_init(phys_addr_t mpmu_phys,phys_addr_t apmu_phys,phys_addr_t apbc_phys)68 void __init pxa168_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
69 phys_addr_t apbc_phys)
70 {
71 struct clk *clk;
72 struct clk *uart_pll;
73 void __iomem *mpmu_base;
74 void __iomem *apmu_base;
75 void __iomem *apbc_base;
76
77 mpmu_base = ioremap(mpmu_phys, SZ_4K);
78 if (!mpmu_base) {
79 pr_err("error to ioremap MPMU base\n");
80 return;
81 }
82
83 apmu_base = ioremap(apmu_phys, SZ_4K);
84 if (!apmu_base) {
85 pr_err("error to ioremap APMU base\n");
86 return;
87 }
88
89 apbc_base = ioremap(apbc_phys, SZ_4K);
90 if (!apbc_base) {
91 pr_err("error to ioremap APBC base\n");
92 return;
93 }
94
95 clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200);
96 clk_register_clkdev(clk, "clk32", NULL);
97
98 clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000);
99 clk_register_clkdev(clk, "vctcxo", NULL);
100
101 clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000);
102 clk_register_clkdev(clk, "pll1", NULL);
103
104 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
105 CLK_SET_RATE_PARENT, 1, 2);
106 clk_register_clkdev(clk, "pll1_2", NULL);
107
108 clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
109 CLK_SET_RATE_PARENT, 1, 2);
110 clk_register_clkdev(clk, "pll1_4", NULL);
111
112 clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
113 CLK_SET_RATE_PARENT, 1, 2);
114 clk_register_clkdev(clk, "pll1_8", NULL);
115
116 clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
117 CLK_SET_RATE_PARENT, 1, 2);
118 clk_register_clkdev(clk, "pll1_16", NULL);
119
120 clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2",
121 CLK_SET_RATE_PARENT, 1, 3);
122 clk_register_clkdev(clk, "pll1_6", NULL);
123
124 clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
125 CLK_SET_RATE_PARENT, 1, 2);
126 clk_register_clkdev(clk, "pll1_12", NULL);
127
128 clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12",
129 CLK_SET_RATE_PARENT, 1, 2);
130 clk_register_clkdev(clk, "pll1_24", NULL);
131
132 clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24",
133 CLK_SET_RATE_PARENT, 1, 2);
134 clk_register_clkdev(clk, "pll1_48", NULL);
135
136 clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48",
137 CLK_SET_RATE_PARENT, 1, 2);
138 clk_register_clkdev(clk, "pll1_96", NULL);
139
140 clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1",
141 CLK_SET_RATE_PARENT, 1, 13);
142 clk_register_clkdev(clk, "pll1_13", NULL);
143
144 clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1",
145 CLK_SET_RATE_PARENT, 2, 3);
146 clk_register_clkdev(clk, "pll1_13_1_5", NULL);
147
148 clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1",
149 CLK_SET_RATE_PARENT, 2, 3);
150 clk_register_clkdev(clk, "pll1_2_1_5", NULL);
151
152 clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1",
153 CLK_SET_RATE_PARENT, 3, 16);
154 clk_register_clkdev(clk, "pll1_3_16", NULL);
155
156 uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
157 mpmu_base + MPMU_UART_PLL,
158 &uart_factor_masks, uart_factor_tbl,
159 ARRAY_SIZE(uart_factor_tbl), &clk_lock);
160 clk_set_rate(uart_pll, 14745600);
161 clk_register_clkdev(uart_pll, "uart_pll", NULL);
162
163 clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5",
164 apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
165 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
166
167 clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5",
168 apbc_base + APBC_TWSI1, 10, 0, &clk_lock);
169 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
170
171 clk = mmp_clk_register_apbc("gpio", "vctcxo",
172 apbc_base + APBC_GPIO, 10, 0, &clk_lock);
173 clk_register_clkdev(clk, NULL, "mmp-gpio");
174
175 clk = mmp_clk_register_apbc("kpc", "clk32",
176 apbc_base + APBC_KPC, 10, 0, &clk_lock);
177 clk_register_clkdev(clk, NULL, "pxa27x-keypad");
178
179 clk = mmp_clk_register_apbc("rtc", "clk32",
180 apbc_base + APBC_RTC, 10, 0, &clk_lock);
181 clk_register_clkdev(clk, NULL, "sa1100-rtc");
182
183 clk = mmp_clk_register_apbc("pwm0", "pll1_48",
184 apbc_base + APBC_PWM0, 10, 0, &clk_lock);
185 clk_register_clkdev(clk, NULL, "pxa168-pwm.0");
186
187 clk = mmp_clk_register_apbc("pwm1", "pll1_48",
188 apbc_base + APBC_PWM1, 10, 0, &clk_lock);
189 clk_register_clkdev(clk, NULL, "pxa168-pwm.1");
190
191 clk = mmp_clk_register_apbc("pwm2", "pll1_48",
192 apbc_base + APBC_PWM2, 10, 0, &clk_lock);
193 clk_register_clkdev(clk, NULL, "pxa168-pwm.2");
194
195 clk = mmp_clk_register_apbc("pwm3", "pll1_48",
196 apbc_base + APBC_PWM3, 10, 0, &clk_lock);
197 clk_register_clkdev(clk, NULL, "pxa168-pwm.3");
198
199 clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
200 ARRAY_SIZE(uart_parent),
201 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
202 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
203 clk_set_parent(clk, uart_pll);
204 clk_register_clkdev(clk, "uart_mux.0", NULL);
205
206 clk = mmp_clk_register_apbc("uart0", "uart0_mux",
207 apbc_base + APBC_UART0, 10, 0, &clk_lock);
208 clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
209
210 clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
211 ARRAY_SIZE(uart_parent),
212 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
213 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
214 clk_set_parent(clk, uart_pll);
215 clk_register_clkdev(clk, "uart_mux.1", NULL);
216
217 clk = mmp_clk_register_apbc("uart1", "uart1_mux",
218 apbc_base + APBC_UART1, 10, 0, &clk_lock);
219 clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
220
221 clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
222 ARRAY_SIZE(uart_parent),
223 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
224 apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
225 clk_set_parent(clk, uart_pll);
226 clk_register_clkdev(clk, "uart_mux.2", NULL);
227
228 clk = mmp_clk_register_apbc("uart2", "uart2_mux",
229 apbc_base + APBC_UART2, 10, 0, &clk_lock);
230 clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
231
232 clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
233 ARRAY_SIZE(ssp_parent),
234 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
235 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
236 clk_register_clkdev(clk, "uart_mux.0", NULL);
237
238 clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", apbc_base + APBC_SSP0,
239 10, 0, &clk_lock);
240 clk_register_clkdev(clk, NULL, "mmp-ssp.0");
241
242 clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
243 ARRAY_SIZE(ssp_parent),
244 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
245 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
246 clk_register_clkdev(clk, "ssp_mux.1", NULL);
247
248 clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", apbc_base + APBC_SSP1,
249 10, 0, &clk_lock);
250 clk_register_clkdev(clk, NULL, "mmp-ssp.1");
251
252 clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
253 ARRAY_SIZE(ssp_parent),
254 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
255 apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
256 clk_register_clkdev(clk, "ssp_mux.2", NULL);
257
258 clk = mmp_clk_register_apbc("ssp2", "ssp1_mux", apbc_base + APBC_SSP2,
259 10, 0, &clk_lock);
260 clk_register_clkdev(clk, NULL, "mmp-ssp.2");
261
262 clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
263 ARRAY_SIZE(ssp_parent),
264 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
265 apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
266 clk_register_clkdev(clk, "ssp_mux.3", NULL);
267
268 clk = mmp_clk_register_apbc("ssp3", "ssp1_mux", apbc_base + APBC_SSP3,
269 10, 0, &clk_lock);
270 clk_register_clkdev(clk, NULL, "mmp-ssp.3");
271
272 clk = clk_register_mux(NULL, "ssp4_mux", ssp_parent,
273 ARRAY_SIZE(ssp_parent),
274 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
275 apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock);
276 clk_register_clkdev(clk, "ssp_mux.4", NULL);
277
278 clk = mmp_clk_register_apbc("ssp4", "ssp1_mux", apbc_base + APBC_SSP4,
279 10, 0, &clk_lock);
280 clk_register_clkdev(clk, NULL, "mmp-ssp.4");
281
282 clk = mmp_clk_register_apmu("dfc", "pll1_4", apmu_base + APMU_DFC,
283 0x19b, &clk_lock);
284 clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
285
286 clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent,
287 ARRAY_SIZE(sdh_parent),
288 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
289 apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
290 clk_register_clkdev(clk, "sdh0_mux", NULL);
291
292 clk = mmp_clk_register_apmu("sdh0", "sdh_mux", apmu_base + APMU_SDH0,
293 0x1b, &clk_lock);
294 clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
295
296 clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent,
297 ARRAY_SIZE(sdh_parent),
298 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
299 apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
300 clk_register_clkdev(clk, "sdh1_mux", NULL);
301
302 clk = mmp_clk_register_apmu("sdh1", "sdh1_mux", apmu_base + APMU_SDH1,
303 0x1b, &clk_lock);
304 clk_register_clkdev(clk, NULL, "sdhci-pxa.1");
305
306 clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB,
307 0x9, &clk_lock);
308 clk_register_clkdev(clk, "usb_clk", NULL);
309
310 clk = mmp_clk_register_apmu("sph", "usb_pll", apmu_base + APMU_USB,
311 0x12, &clk_lock);
312 clk_register_clkdev(clk, "sph_clk", NULL);
313
314 clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
315 ARRAY_SIZE(disp_parent),
316 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
317 apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
318 clk_register_clkdev(clk, "disp_mux.0", NULL);
319
320 clk = mmp_clk_register_apmu("disp0", "disp0_mux",
321 apmu_base + APMU_DISP0, 0x1b, &clk_lock);
322 clk_register_clkdev(clk, "fnclk", "mmp-disp.0");
323
324 clk = mmp_clk_register_apmu("disp0_hclk", "disp0_mux",
325 apmu_base + APMU_DISP0, 0x24, &clk_lock);
326 clk_register_clkdev(clk, "hclk", "mmp-disp.0");
327
328 clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
329 ARRAY_SIZE(ccic_parent),
330 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
331 apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
332 clk_register_clkdev(clk, "ccic_mux.0", NULL);
333
334 clk = mmp_clk_register_apmu("ccic0", "ccic0_mux",
335 apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
336 clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
337
338 clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
339 ARRAY_SIZE(ccic_phy_parent),
340 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
341 apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
342 clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
343
344 clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
345 apmu_base + APMU_CCIC0, 0x24, &clk_lock);
346 clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
347
348 clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux",
349 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
350 10, 5, 0, &clk_lock);
351 clk_register_clkdev(clk, "sphyclk_div", NULL);
352
353 clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
354 apmu_base + APMU_CCIC0, 0x300, &clk_lock);
355 clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
356 }
357
