256 	clk_set_parent(clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL],  in mmdc_ch1_disable()
263 	clk_set_parent(clk[IMX6QDL_CLK_PERIPH2], clk[IMX6QDL_CLK_PERIPH2_CLK2]);  in mmdc_ch1_disable()
280 	clk_set_parent(clk[IMX6QDL_CLK_PERIPH2], clk[IMX6QDL_CLK_PERIPH2_PRE]);  in mmdc_ch1_reenable()
462 	clk_set_parent(clk[IMX6QDL_PLL1_BYPASS], clk[IMX6QDL_CLK_PLL1]);  in imx6q_clocks_init()
463 	clk_set_parent(clk[IMX6QDL_PLL2_BYPASS], clk[IMX6QDL_CLK_PLL2]);  in imx6q_clocks_init()
464 	clk_set_parent(clk[IMX6QDL_PLL3_BYPASS], clk[IMX6QDL_CLK_PLL3]);  in imx6q_clocks_init()
465 	clk_set_parent(clk[IMX6QDL_PLL4_BYPASS], clk[IMX6QDL_CLK_PLL4]);  in imx6q_clocks_init()
466 	clk_set_parent(clk[IMX6QDL_PLL5_BYPASS], clk[IMX6QDL_CLK_PLL5]);  in imx6q_clocks_init()
467 	clk_set_parent(clk[IMX6QDL_PLL6_BYPASS], clk[IMX6QDL_CLK_PLL6]);  in imx6q_clocks_init()
468 	clk_set_parent(clk[IMX6QDL_PLL7_BYPASS], clk[IMX6QDL_CLK_PLL7]);  in imx6q_clocks_init()
856 		clk_set_parent(clk[IMX6QDL_CLK_IPU1_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]);  in imx6q_clocks_init()
858 	clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);  in imx6q_clocks_init()
859 	clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);  in imx6q_clocks_init()
860 	clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);  in imx6q_clocks_init()
861 	clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);  in imx6q_clocks_init()
862 	clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_SEL], clk[IMX6QDL_CLK_IPU1_DI0_PRE]);  in imx6q_clocks_init()
863 	clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_SEL], clk[IMX6QDL_CLK_IPU1_DI1_PRE]);  in imx6q_clocks_init()
864 	clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], clk[IMX6QDL_CLK_IPU2_DI0_PRE]);  in imx6q_clocks_init()
865 	clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_SEL], clk[IMX6QDL_CLK_IPU2_DI1_PRE]);  in imx6q_clocks_init()
872 	clk_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]);  in imx6q_clocks_init()
883 	ret = clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]);  in imx6q_clocks_init()
885 		ret = clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]);  in imx6q_clocks_init()
890 	clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]);  in imx6q_clocks_init()
894 		clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]);  in imx6q_clocks_init()
901 		clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL],  in imx6q_clocks_init()
903 		clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL],  in imx6q_clocks_init()
906 		clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL],  in imx6q_clocks_init()
908 		clk_set_parent(clk[IMX6QDL_CLK_GPU3D_SHADER_SEL],  in imx6q_clocks_init()
910 		clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL],  in imx6q_clocks_init()