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Searched refs:RREG32 (Results 1 – 25 of 127) sorted by relevance

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/Linux-v4.19/drivers/gpu/drm/radeon/
Dradeon_bios.c256 bus_cntl = RREG32(R600_BUS_CNTL); in ni_read_disabled_bios()
257 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); in ni_read_disabled_bios()
258 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); in ni_read_disabled_bios()
259 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); in ni_read_disabled_bios()
260 rom_cntl = RREG32(R600_ROM_CNTL); in ni_read_disabled_bios()
302 viph_control = RREG32(RADEON_VIPH_CONTROL); in r700_read_disabled_bios()
303 bus_cntl = RREG32(R600_BUS_CNTL); in r700_read_disabled_bios()
304 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); in r700_read_disabled_bios()
305 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); in r700_read_disabled_bios()
306 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); in r700_read_disabled_bios()
[all …]
Dradeon_legacy_encoders.c58 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); in radeon_legacy_lvds_update()
86 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN); in radeon_legacy_lvds_update()
89 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); in radeon_legacy_lvds_update()
94 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); in radeon_legacy_lvds_update()
189 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); in radeon_legacy_lvds_mode_set()
192 lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); in radeon_legacy_lvds_mode_set()
199 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); in radeon_legacy_lvds_mode_set()
210 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); in radeon_legacy_lvds_mode_set()
280 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> in radeon_legacy_get_backlight_level()
354 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> in radeon_legacy_backlight_get_brightness()
[all …]
Dvce_v2_0.c43 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
47 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
51 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
57 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
62 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
67 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
77 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_dyn_cg()
87 orig = tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_dyn_cg()
93 orig = tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_dyn_cg()
134 tmp = RREG32(VCE_CLOCK_GATING_A); in vce_v2_0_init_cg()
[all …]
Dradeon_i2c.c129 temp = RREG32(rec->mask_clk_reg); in pre_xfer()
135 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; in pre_xfer()
138 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; in pre_xfer()
142 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; in pre_xfer()
145 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; in pre_xfer()
149 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; in pre_xfer()
151 temp = RREG32(rec->mask_clk_reg); in pre_xfer()
153 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; in pre_xfer()
155 temp = RREG32(rec->mask_data_reg); in pre_xfer()
168 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; in post_xfer()
[all …]
Dvce_v1_0.c63 return RREG32(VCE_RB_RPTR); in vce_v1_0_get_rptr()
65 return RREG32(VCE_RB_RPTR2); in vce_v1_0_get_rptr()
80 return RREG32(VCE_RB_WPTR); in vce_v1_0_get_wptr()
82 return RREG32(VCE_RB_WPTR2); in vce_v1_0_get_wptr()
107 tmp = RREG32(VCE_CLOCK_GATING_A); in vce_v1_0_enable_mgcg()
111 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v1_0_enable_mgcg()
116 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v1_0_enable_mgcg()
120 tmp = RREG32(VCE_CLOCK_GATING_A); in vce_v1_0_enable_mgcg()
124 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v1_0_enable_mgcg()
129 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v1_0_enable_mgcg()
[all …]
Drs600.c58 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) in avivo_is_in_vblank()
68 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); in avivo_is_counter_moving()
69 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); in avivo_is_counter_moving()
92 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) in avivo_wait_for_vblank()
116 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rs600_page_flip()
133 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rs600_page_flip()
149 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & in rs600_page_flip_pending()
227 tmp = RREG32(voltage->gpio.reg); in rs600_pm_misc()
236 tmp = RREG32(voltage->gpio.reg); in rs600_pm_misc()
322 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); in rs600_pm_prepare()
[all …]
Drv730_dpm.c203 RREG32(CG_SPLL_FUNC_CNTL); in rv730_read_clock_registers()
205 RREG32(CG_SPLL_FUNC_CNTL_2); in rv730_read_clock_registers()
207 RREG32(CG_SPLL_FUNC_CNTL_3); in rv730_read_clock_registers()
209 RREG32(CG_SPLL_SPREAD_SPECTRUM); in rv730_read_clock_registers()
211 RREG32(CG_SPLL_SPREAD_SPECTRUM_2); in rv730_read_clock_registers()
214 RREG32(TCI_MCLK_PWRMGT_CNTL); in rv730_read_clock_registers()
216 RREG32(TCI_DLL_CNTL); in rv730_read_clock_registers()
218 RREG32(CG_MPLL_FUNC_CNTL); in rv730_read_clock_registers()
220 RREG32(CG_MPLL_FUNC_CNTL_2); in rv730_read_clock_registers()
222 RREG32(CG_MPLL_FUNC_CNTL_3); in rv730_read_clock_registers()
[all …]
Dr600.c121 r = RREG32(R600_RCU_DATA); in r600_rcu_rreg()
143 r = RREG32(R600_UVD_CTX_DATA); in r600_uvd_ctx_rreg()
177 *val = RREG32(reg); in r600_get_allowed_info_register()
346 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> in rv6xx_get_temp()
791 if (RREG32(GRBM_STATUS) & GUI_ACTIVE) in r600_gui_idle()
805 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
809 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
813 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
817 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
822 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
[all …]
Drs400.c153 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; in rs400_gart_enable()
157 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; in rs400_gart_enable()
244 tmp = RREG32(RADEON_MC_STATUS); in rs400_mc_wait_for_idle()
259 RREG32(RADEON_MC_STATUS)); in rs400_gpu_init()
273 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; in rs400_mc_init()
287 r = RREG32(RS480_NB_MC_DATA); in rs400_mc_rreg()
312 tmp = RREG32(RADEON_HOST_PATH_CNTL); in rs400_debugfs_gart_info()
314 tmp = RREG32(RADEON_BUS_CNTL); in rs400_debugfs_gart_info()
327 tmp = RREG32(RS690_HDP_FB_LOCATION); in rs400_debugfs_gart_info()
330 tmp = RREG32(RADEON_AGP_BASE); in rs400_debugfs_gart_info()
[all …]
Dr100.c74 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR) in r100_is_in_vblank()
79 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR) in r100_is_in_vblank()
91 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
92 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
94 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
95 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
119 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN)) in r100_wait_for_vblank()
122 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN)) in r100_wait_for_vblank()
168 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) in r100_page_flip()
194 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & in r100_page_flip_pending()
[all …]
Dcik.c174 *val = RREG32(reg); in cik_get_allowed_info_register()
191 r = RREG32(CIK_DIDT_IND_DATA); in cik_didt_rreg()
253 (void)RREG32(PCIE_INDEX); in cik_pciep_rreg()
254 r = RREG32(PCIE_DATA); in cik_pciep_rreg()
265 (void)RREG32(PCIE_INDEX); in cik_pciep_wreg()
267 (void)RREG32(PCIE_DATA); in cik_pciep_wreg()
1911 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; in ci_mc_load_microcode()
1929 tmp = RREG32(MC_SEQ_MISC0); in ci_mc_load_microcode()
1952 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0) in ci_mc_load_microcode()
1957 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1) in ci_mc_load_microcode()
[all …]
Dr420.c98 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); in r420_pipes_init()
133 tmp = RREG32(R300_DST_PIPE_CONFIG); in r420_pipes_init()
137 RREG32(R300_RB2D_DSTCACHE_MODE) | in r420_pipes_init()
146 tmp = RREG32(RV530_GB_PIPE_SELECT2); in r420_pipes_init()
165 r = RREG32(R_0001FC_MC_IND_DATA); in r420_mc_rreg()
283 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); in r420_startup()
315 RREG32(R_000E40_RBBM_STATUS), in r420_resume()
316 RREG32(R_0007C0_CP_STAT)); in r420_resume()
406 RREG32(R_000E40_RBBM_STATUS), in r420_init()
407 RREG32(R_0007C0_CP_STAT)); in r420_init()
[all …]
/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dgmc_v8_0.c177 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v8_0_mc_stop()
195 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v8_0_mc_resume()
295 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v8_0_tonga_mc_load_microcode()
318 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v8_0_tonga_mc_load_microcode()
324 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v8_0_tonga_mc_load_microcode()
351 data = RREG32(mmMC_SEQ_IO_DEBUG_DATA); in gmc_v8_0_polaris_mc_load_microcode()
371 data = RREG32(mmMC_SEQ_MISC0); in gmc_v8_0_polaris_mc_load_microcode()
395 data = RREG32(mmMC_SEQ_MISC0); in gmc_v8_0_polaris_mc_load_microcode()
410 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; in gmc_v8_0_vram_gtt_location()
445 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v8_0_mc_program()
[all …]
Damdgpu_i2c.c50 temp = RREG32(rec->mask_clk_reg); in amdgpu_i2c_pre_xfer()
56 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; in amdgpu_i2c_pre_xfer()
59 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; in amdgpu_i2c_pre_xfer()
63 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; in amdgpu_i2c_pre_xfer()
66 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; in amdgpu_i2c_pre_xfer()
70 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; in amdgpu_i2c_pre_xfer()
72 temp = RREG32(rec->mask_clk_reg); in amdgpu_i2c_pre_xfer()
74 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; in amdgpu_i2c_pre_xfer()
76 temp = RREG32(rec->mask_data_reg); in amdgpu_i2c_pre_xfer()
89 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; in amdgpu_i2c_post_xfer()
[all …]
Dgmc_v7_0.c92 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v7_0_mc_stop()
110 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v7_0_mc_resume()
199 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v7_0_mc_load_microcode()
222 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v7_0_mc_load_microcode()
228 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v7_0_mc_load_microcode()
241 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; in gmc_v7_0_vram_gtt_location()
276 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v7_0_mc_program()
281 tmp = RREG32(mmVGA_RENDER_CONTROL); in gmc_v7_0_mc_program()
301 tmp = RREG32(mmHDP_MISC_CNTL); in gmc_v7_0_mc_program()
305 tmp = RREG32(mmHDP_HOST_PATH_CNTL); in gmc_v7_0_mc_program()
[all …]
Dvce_v2_0.c60 return RREG32(mmVCE_RB_RPTR); in vce_v2_0_ring_get_rptr()
62 return RREG32(mmVCE_RB_RPTR2); in vce_v2_0_ring_get_rptr()
77 return RREG32(mmVCE_RB_WPTR); in vce_v2_0_ring_get_wptr()
79 return RREG32(mmVCE_RB_WPTR2); in vce_v2_0_ring_get_wptr()
105 uint32_t status = RREG32(mmVCE_LMI_STATUS); in vce_v2_0_lmi_clean()
122 uint32_t status = RREG32(mmVCE_STATUS); in vce_v2_0_firmware_loaded()
151 tmp = RREG32(mmVCE_CLOCK_GATING_A); in vce_v2_0_init_cg()
157 tmp = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v2_0_init_cg()
162 tmp = RREG32(mmVCE_CLOCK_GATING_B); in vce_v2_0_init_cg()
208 return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK); in vce_v2_0_is_idle()
[all …]
Dgmc_v6_0.c76 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v6_0_mc_stop()
95 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v6_0_mc_resume()
133 if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58) in gmc_v6_0_init_microcode()
180 running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK; in gmc_v6_0_mc_load_microcode()
205 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK) in gmc_v6_0_mc_load_microcode()
210 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK) in gmc_v6_0_mc_load_microcode()
223 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; in gmc_v6_0_vram_gtt_location()
252 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v6_0_mc_program()
257 tmp = RREG32(mmVGA_RENDER_CONTROL); in gmc_v6_0_mc_program()
284 tmp = RREG32(mmMC_ARB_RAMCFG); in gmc_v6_0_mc_init()
[all …]
Dcz_ih.c60 u32 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_enable_interrupts()
61 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cz_ih_enable_interrupts()
79 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cz_ih_disable_interrupts()
80 u32 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_disable_interrupts()
115 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); in cz_ih_irq_init()
147 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_irq_init()
203 tmp = RREG32(mmIH_RB_CNTL); in cz_ih_get_wptr()
358 u32 tmp = RREG32(mmSRBM_STATUS); in cz_ih_is_idle()
374 tmp = RREG32(mmSRBM_STATUS); in cz_ih_wait_for_idle()
386 u32 tmp = RREG32(mmSRBM_STATUS); in cz_ih_soft_reset()
[all …]
Diceland_ih.c60 u32 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_enable_interrupts()
61 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in iceland_ih_enable_interrupts()
79 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in iceland_ih_disable_interrupts()
80 u32 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_disable_interrupts()
115 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); in iceland_ih_irq_init()
147 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_irq_init()
203 tmp = RREG32(mmIH_RB_CNTL); in iceland_ih_get_wptr()
358 u32 tmp = RREG32(mmSRBM_STATUS); in iceland_ih_is_idle()
374 tmp = RREG32(mmSRBM_STATUS); in iceland_ih_wait_for_idle()
386 u32 tmp = RREG32(mmSRBM_STATUS); in iceland_ih_soft_reset()
[all …]
Dcik_ih.c60 u32 ih_cntl = RREG32(mmIH_CNTL); in cik_ih_enable_interrupts()
61 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cik_ih_enable_interrupts()
79 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cik_ih_disable_interrupts()
80 u32 ih_cntl = RREG32(mmIH_CNTL); in cik_ih_disable_interrupts()
115 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); in cik_ih_irq_init()
201 tmp = RREG32(mmIH_RB_CNTL); in cik_ih_get_wptr()
379 u32 tmp = RREG32(mmSRBM_STATUS); in cik_ih_is_idle()
395 tmp = RREG32(mmSRBM_STATUS) & SRBM_STATUS__IH_BUSY_MASK; in cik_ih_wait_for_idle()
408 u32 tmp = RREG32(mmSRBM_STATUS); in cik_ih_soft_reset()
414 tmp = RREG32(mmSRBM_SOFT_RESET); in cik_ih_soft_reset()
[all …]
Dsi_ih.c33 u32 ih_cntl = RREG32(IH_CNTL); in si_ih_enable_interrupts()
34 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_ih_enable_interrupts()
45 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_ih_disable_interrupts()
46 u32 ih_cntl = RREG32(IH_CNTL); in si_ih_disable_interrupts()
66 interrupt_cntl = RREG32(INTERRUPT_CNTL); in si_ih_irq_init()
114 tmp = RREG32(IH_RB_CNTL); in si_ih_get_wptr()
223 u32 tmp = RREG32(SRBM_STATUS); in si_ih_is_idle()
249 u32 tmp = RREG32(SRBM_STATUS); in si_ih_soft_reset()
255 tmp = RREG32(SRBM_SOFT_RESET); in si_ih_soft_reset()
259 tmp = RREG32(SRBM_SOFT_RESET); in si_ih_soft_reset()
[all …]
Dvce_v3_0.c91 v = RREG32(mmVCE_RB_RPTR); in vce_v3_0_ring_get_rptr()
93 v = RREG32(mmVCE_RB_RPTR2); in vce_v3_0_ring_get_rptr()
95 v = RREG32(mmVCE_RB_RPTR3); in vce_v3_0_ring_get_rptr()
123 v = RREG32(mmVCE_RB_WPTR); in vce_v3_0_ring_get_wptr()
125 v = RREG32(mmVCE_RB_WPTR2); in vce_v3_0_ring_get_wptr()
127 v = RREG32(mmVCE_RB_WPTR3); in vce_v3_0_ring_get_wptr()
183 data = RREG32(mmVCE_CLOCK_GATING_B); in vce_v3_0_set_vce_sw_clock_gating()
188 data = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v3_0_set_vce_sw_clock_gating()
193 data = RREG32(mmVCE_UENC_CLOCK_GATING_2); in vce_v3_0_set_vce_sw_clock_gating()
198 data = RREG32(mmVCE_UENC_REG_CLOCK_GATING); in vce_v3_0_set_vce_sw_clock_gating()
[all …]
Dsi_smc.c86 original_data = RREG32(SMC_IND_DATA_0); in amdgpu_si_copy_bytes_to_smc()
124 RREG32(CB_CGTT_SCLK_CTRL); in amdgpu_si_reset_smc()
125 RREG32(CB_CGTT_SCLK_CTRL); in amdgpu_si_reset_smc()
126 RREG32(CB_CGTT_SCLK_CTRL); in amdgpu_si_reset_smc()
127 RREG32(CB_CGTT_SCLK_CTRL); in amdgpu_si_reset_smc()
176 tmp = RREG32(SMC_RESP_0); in amdgpu_si_send_msg_to_smc()
182 return (PPSMC_Result)RREG32(SMC_RESP_0); in amdgpu_si_send_msg_to_smc()
254 *value = RREG32(SMC_IND_DATA_0); in amdgpu_si_read_smc_sram_dword()
Dvce_v4_0.c66 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR)); in vce_v4_0_ring_get_rptr()
68 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2)); in vce_v4_0_ring_get_rptr()
70 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3)); in vce_v4_0_ring_get_rptr()
88 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR)); in vce_v4_0_ring_get_wptr()
90 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2)); in vce_v4_0_ring_get_wptr()
92 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3)); in vce_v4_0_ring_get_wptr()
131 RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS)); in vce_v4_0_firmware_loaded()
167 data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_VMID)); in vce_v4_0_mmsch_start()
186 data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP)); in vce_v4_0_mmsch_start()
190 data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP)); in vce_v4_0_mmsch_start()
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Dgfx_v7_0.c1624 data = RREG32(mmCC_RB_BACKEND_DISABLE); in gfx_v7_0_get_rb_active_bitmap()
1625 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); in gfx_v7_0_get_rb_active_bitmap()
1830 RREG32(mmCC_RB_BACKEND_DISABLE); in gfx_v7_0_setup_rb()
1832 RREG32(mmGC_USER_RB_BACKEND_DISABLE); in gfx_v7_0_setup_rb()
1834 RREG32(mmPA_SC_RASTER_CONFIG); in gfx_v7_0_setup_rb()
1836 RREG32(mmPA_SC_RASTER_CONFIG_1); in gfx_v7_0_setup_rb()
1966 tmp = RREG32(mmSPI_CONFIG_CNTL); in gfx_v7_0_gpu_init()
1974 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff; in gfx_v7_0_gpu_init()
1978 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c; in gfx_v7_0_gpu_init()
1982 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000; in gfx_v7_0_gpu_init()
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