92 	blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);  in gmc_v7_0_mc_stop()
110 	tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);  in gmc_v7_0_mc_resume()
199 	running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);  in gmc_v7_0_mc_load_microcode()
222 			if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),  in gmc_v7_0_mc_load_microcode()
228 			if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),  in gmc_v7_0_mc_load_microcode()
241 	u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;  in gmc_v7_0_vram_gtt_location()
276 		tmp = RREG32(mmVGA_HDP_CONTROL);  in gmc_v7_0_mc_program()
281 		tmp = RREG32(mmVGA_RENDER_CONTROL);  in gmc_v7_0_mc_program()
301 	tmp = RREG32(mmHDP_MISC_CNTL);  in gmc_v7_0_mc_program()
305 	tmp = RREG32(mmHDP_HOST_PATH_CNTL);  in gmc_v7_0_mc_program()
328 		tmp = RREG32(mmMC_ARB_RAMCFG);  in gmc_v7_0_mc_init()
334 		tmp = RREG32(mmMC_SHARED_CHMAP);  in gmc_v7_0_mc_init()
368 	adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;  in gmc_v7_0_mc_init()
369 	adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;  in gmc_v7_0_mc_init()
381 		adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;  in gmc_v7_0_mc_init()
518 	tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v7_0_set_fault_enable_default()
549 	tmp = RREG32(mmVM_PRT_CNTL);  in gmc_v7_0_set_prt()
615 	tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);  in gmc_v7_0_gart_enable()
623 	tmp = RREG32(mmVM_L2_CNTL);  in gmc_v7_0_gart_enable()
637 	tmp = RREG32(mmVM_L2_CNTL3);  in gmc_v7_0_gart_enable()
649 	tmp = RREG32(mmVM_CONTEXT0_CNTL);  in gmc_v7_0_gart_enable()
679 	tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v7_0_gart_enable()
691 		tmp = RREG32(mmCHUB_CONTROL);  in gmc_v7_0_gart_enable()
736 	tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);  in gmc_v7_0_gart_disable()
742 	tmp = RREG32(mmVM_L2_CNTL);  in gmc_v7_0_gart_disable()
822 		orig = data = RREG32(mc_cg_registers[i]);  in gmc_v7_0_enable_mc_ls()
839 		orig = data = RREG32(mc_cg_registers[i]);  in gmc_v7_0_enable_mc_mgcg()
877 	orig = data = RREG32(mmHDP_HOST_PATH_CNTL);  in gmc_v7_0_enable_hdp_mgcg()
893 	orig = data = RREG32(mmHDP_MEM_POWER_LS);  in gmc_v7_0_enable_hdp_ls()
958 	u32 d1vga_control = RREG32(mmD1VGA_CONTROL);  in gmc_v7_0_get_vbios_fb_size()
964 		u32 viewport = RREG32(mmVIEWPORT_SIZE);  in gmc_v7_0_get_vbios_fb_size()
984 		u32 tmp = RREG32(mmMC_SEQ_MISC0);  in gmc_v7_0_sw_init()
1061 		u64 tmp = RREG32(mmMC_VM_FB_OFFSET);  in gmc_v7_0_sw_init()
1154 	u32 tmp = RREG32(mmSRBM_STATUS);  in gmc_v7_0_is_idle()
1171 		tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |  in gmc_v7_0_wait_for_idle()
1188 	u32 tmp = RREG32(mmSRBM_STATUS);  in gmc_v7_0_soft_reset()
1208 		tmp = RREG32(mmSRBM_SOFT_RESET);  in gmc_v7_0_soft_reset()
1212 		tmp = RREG32(mmSRBM_SOFT_RESET);  in gmc_v7_0_soft_reset()
1218 		tmp = RREG32(mmSRBM_SOFT_RESET);  in gmc_v7_0_soft_reset()
1246 		tmp = RREG32(mmVM_CONTEXT0_CNTL);  in gmc_v7_0_vm_fault_interrupt_state()
1250 		tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v7_0_vm_fault_interrupt_state()
1256 		tmp = RREG32(mmVM_CONTEXT0_CNTL);  in gmc_v7_0_vm_fault_interrupt_state()
1260 		tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v7_0_vm_fault_interrupt_state()
1277 	addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);  in gmc_v7_0_process_interrupt()
1278 	status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);  in gmc_v7_0_process_interrupt()
1279 	mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);  in gmc_v7_0_process_interrupt()