91 		v = RREG32(mmVCE_RB_RPTR);  in vce_v3_0_ring_get_rptr()
93 		v = RREG32(mmVCE_RB_RPTR2);  in vce_v3_0_ring_get_rptr()
95 		v = RREG32(mmVCE_RB_RPTR3);  in vce_v3_0_ring_get_rptr()
123 		v = RREG32(mmVCE_RB_WPTR);  in vce_v3_0_ring_get_wptr()
125 		v = RREG32(mmVCE_RB_WPTR2);  in vce_v3_0_ring_get_wptr()
127 		v = RREG32(mmVCE_RB_WPTR3);  in vce_v3_0_ring_get_wptr()
183 		data = RREG32(mmVCE_CLOCK_GATING_B);  in vce_v3_0_set_vce_sw_clock_gating()
188 		data = RREG32(mmVCE_UENC_CLOCK_GATING);  in vce_v3_0_set_vce_sw_clock_gating()
193 		data = RREG32(mmVCE_UENC_CLOCK_GATING_2);  in vce_v3_0_set_vce_sw_clock_gating()
198 		data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);  in vce_v3_0_set_vce_sw_clock_gating()
202 		data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL);  in vce_v3_0_set_vce_sw_clock_gating()
209 		data = RREG32(mmVCE_CLOCK_GATING_B);  in vce_v3_0_set_vce_sw_clock_gating()
214 		data = RREG32(mmVCE_UENC_CLOCK_GATING);  in vce_v3_0_set_vce_sw_clock_gating()
218 		data = RREG32(mmVCE_UENC_CLOCK_GATING_2);  in vce_v3_0_set_vce_sw_clock_gating()
222 		data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);  in vce_v3_0_set_vce_sw_clock_gating()
226 		data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL);  in vce_v3_0_set_vce_sw_clock_gating()
242 			uint32_t status = RREG32(mmVCE_STATUS);  in vce_v3_0_firmware_loaded()
589 	return !(RREG32(mmSRBM_STATUS2) & mask);  in vce_v3_0_is_idle()
630 	if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {  in vce_v3_0_check_soft_reset()
635 	if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {  in vce_v3_0_check_soft_reset()
663 		tmp = RREG32(mmSRBM_SOFT_RESET);  in vce_v3_0_soft_reset()
667 		tmp = RREG32(mmSRBM_SOFT_RESET);  in vce_v3_0_soft_reset()
673 		tmp = RREG32(mmSRBM_SOFT_RESET);  in vce_v3_0_soft_reset()
764 			uint32_t data = RREG32(mmVCE_CLOCK_GATING_A);  in vce_v3_0_set_clockgating_state()
770 			data = RREG32(mmVCE_UENC_CLOCK_GATING);  in vce_v3_0_set_clockgating_state()
832 	data = RREG32(mmVCE_CLOCK_GATING_A);  in vce_v3_0_get_clockgating_state()