Lines Matching refs:RREG32
1624 data = RREG32(mmCC_RB_BACKEND_DISABLE); in gfx_v7_0_get_rb_active_bitmap()
1625 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); in gfx_v7_0_get_rb_active_bitmap()
1830 RREG32(mmCC_RB_BACKEND_DISABLE); in gfx_v7_0_setup_rb()
1832 RREG32(mmGC_USER_RB_BACKEND_DISABLE); in gfx_v7_0_setup_rb()
1834 RREG32(mmPA_SC_RASTER_CONFIG); in gfx_v7_0_setup_rb()
1836 RREG32(mmPA_SC_RASTER_CONFIG_1); in gfx_v7_0_setup_rb()
1966 tmp = RREG32(mmSPI_CONFIG_CNTL); in gfx_v7_0_gpu_init()
1974 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff; in gfx_v7_0_gpu_init()
1978 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c; in gfx_v7_0_gpu_init()
1982 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000; in gfx_v7_0_gpu_init()
2015 tmp = RREG32(mmSPI_ARB_PRIORITY); in gfx_v7_0_gpu_init()
2084 tmp = RREG32(scratch); in gfx_v7_0_ring_test_ring()
2348 tmp = RREG32(scratch); in gfx_v7_0_ring_test_ib()
2635 return RREG32(mmCP_RB0_WPTR); in gfx_v7_0_ring_get_wptr_gfx()
2643 (void)RREG32(mmCP_RB0_WPTR); in gfx_v7_0_ring_set_wptr_gfx()
2863 tmp = RREG32(mmCP_HPD_EOP_CONTROL); in gfx_v7_0_compute_pipe_init()
2877 if (RREG32(mmCP_HQD_ACTIVE) & 1) { in gfx_v7_0_mqd_deactivate()
2880 if (!(RREG32(mmCP_HQD_ACTIVE) & 1)) in gfx_v7_0_mqd_deactivate()
2915 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v7_0_mqd_init()
2926 mqd->cp_mqd_control = RREG32(mmCP_MQD_CONTROL); in gfx_v7_0_mqd_init()
2935 mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL); in gfx_v7_0_mqd_init()
2970 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v7_0_mqd_init()
2989 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); in gfx_v7_0_mqd_init()
2995 mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL); in gfx_v7_0_mqd_init()
2996 mqd->cp_hqd_ib_base_addr_lo = RREG32(mmCP_HQD_IB_BASE_ADDR); in gfx_v7_0_mqd_init()
2997 mqd->cp_hqd_ib_base_addr_hi = RREG32(mmCP_HQD_IB_BASE_ADDR_HI); in gfx_v7_0_mqd_init()
2998 mqd->cp_hqd_ib_rptr = RREG32(mmCP_HQD_IB_RPTR); in gfx_v7_0_mqd_init()
2999 mqd->cp_hqd_persistent_state = RREG32(mmCP_HQD_PERSISTENT_STATE); in gfx_v7_0_mqd_init()
3000 mqd->cp_hqd_sema_cmd = RREG32(mmCP_HQD_SEMA_CMD); in gfx_v7_0_mqd_init()
3001 mqd->cp_hqd_msg_type = RREG32(mmCP_HQD_MSG_TYPE); in gfx_v7_0_mqd_init()
3002 mqd->cp_hqd_atomic0_preop_lo = RREG32(mmCP_HQD_ATOMIC0_PREOP_LO); in gfx_v7_0_mqd_init()
3003 mqd->cp_hqd_atomic0_preop_hi = RREG32(mmCP_HQD_ATOMIC0_PREOP_HI); in gfx_v7_0_mqd_init()
3004 mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO); in gfx_v7_0_mqd_init()
3005 mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI); in gfx_v7_0_mqd_init()
3006 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); in gfx_v7_0_mqd_init()
3007 mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM); in gfx_v7_0_mqd_init()
3008 mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY); in gfx_v7_0_mqd_init()
3009 mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY); in gfx_v7_0_mqd_init()
3010 mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR); in gfx_v7_0_mqd_init()
3026 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL); in gfx_v7_0_mqd_commit()
3087 tmp = RREG32(mmCP_CPF_DEBUG); in gfx_v7_0_cp_compute_resume()
3141 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_enable_gui_idle_interrupt()
3378 tmp = RREG32(mmRLC_LB_CNTL); in gfx_v7_0_enable_lbpw()
3396 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0) in gfx_v7_0_wait_for_rlc_serdes()
3410 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) in gfx_v7_0_wait_for_rlc_serdes()
3420 tmp = RREG32(mmRLC_CNTL); in gfx_v7_0_update_rlc()
3429 orig = data = RREG32(mmRLC_CNTL); in gfx_v7_0_halt_rlc()
3438 if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0) in gfx_v7_0_halt_rlc()
3459 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask) in gfx_v7_0_enter_rlc_safe_mode()
3465 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0) in gfx_v7_0_enter_rlc_safe_mode()
3513 u32 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v7_0_rlc_reset()
3551 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc; in gfx_v7_0_rlc_resume()
3594 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); in gfx_v7_0_enable_cgcg()
3620 RREG32(mmCB_CGTT_SCLK_CTRL); in gfx_v7_0_enable_cgcg()
3621 RREG32(mmCB_CGTT_SCLK_CTRL); in gfx_v7_0_enable_cgcg()
3622 RREG32(mmCB_CGTT_SCLK_CTRL); in gfx_v7_0_enable_cgcg()
3623 RREG32(mmCB_CGTT_SCLK_CTRL); in gfx_v7_0_enable_cgcg()
3640 orig = data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v7_0_enable_mgcg()
3647 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); in gfx_v7_0_enable_mgcg()
3667 orig = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v7_0_enable_mgcg()
3682 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); in gfx_v7_0_enable_mgcg()
3687 data = RREG32(mmRLC_MEM_SLP_CNTL); in gfx_v7_0_enable_mgcg()
3693 data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v7_0_enable_mgcg()
3699 orig = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v7_0_enable_mgcg()
3738 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_sclk_slowdown_on_pu()
3752 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_sclk_slowdown_on_pd()
3765 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_cp_pg()
3778 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gds_pg()
3861 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gfx_cgpg()
3866 orig = data = RREG32(mmRLC_AUTO_PG_CTRL); in gfx_v7_0_enable_gfx_cgpg()
3871 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gfx_cgpg()
3876 orig = data = RREG32(mmRLC_AUTO_PG_CTRL); in gfx_v7_0_enable_gfx_cgpg()
3881 data = RREG32(mmDB_RENDER_CONTROL); in gfx_v7_0_enable_gfx_cgpg()
3903 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG); in gfx_v7_0_get_cu_active_bitmap()
3904 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); in gfx_v7_0_get_cu_active_bitmap()
3920 tmp = RREG32(mmRLC_MAX_PG_CU); in gfx_v7_0_init_ao_cu_mask()
3931 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gfx_static_mgpg()
3945 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gfx_dynamic_mgpg()
3978 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_init_gfx_cgpg()
3986 data = RREG32(mmCP_RB_WPTR_POLL_CNTL); in gfx_v7_0_init_gfx_cgpg()
3994 data = RREG32(mmRLC_PG_DELAY_2); in gfx_v7_0_init_gfx_cgpg()
3999 data = RREG32(mmRLC_AUTO_PG_CTRL); in gfx_v7_0_init_gfx_cgpg()
4161 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | in gfx_v7_0_get_gpu_clock_counter()
4162 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); in gfx_v7_0_get_gpu_clock_counter()
4222 return RREG32(mmSQ_IND_DATA); in wave_read_ind()
4237 *(out++) = RREG32(mmSQ_IND_DATA); in wave_read_regs()
4403 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); in gfx_v7_0_gpu_early_init()
4404 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); in gfx_v7_0_gpu_early_init()
4411 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); in gfx_v7_0_gpu_early_init()
4415 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING); in gfx_v7_0_gpu_early_init()
4688 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) in gfx_v7_0_is_idle()
4702 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK; in gfx_v7_0_wait_for_idle()
4718 tmp = RREG32(mmGRBM_STATUS); in gfx_v7_0_soft_reset()
4734 tmp = RREG32(mmGRBM_STATUS2); in gfx_v7_0_soft_reset()
4739 tmp = RREG32(mmSRBM_STATUS); in gfx_v7_0_soft_reset()
4758 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
4762 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
4768 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
4772 tmp = RREG32(mmSRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
4776 tmp = RREG32(mmSRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
4782 tmp = RREG32(mmSRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
4797 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state()
4802 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state()
4848 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v7_0_set_compute_eop_interrupt_state()
4853 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v7_0_set_compute_eop_interrupt_state()
4871 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_priv_reg_fault_state()
4876 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_priv_reg_fault_state()
4896 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_priv_inst_fault_state()
4901 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_priv_inst_fault_state()
5162 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE); in gfx_v7_0_set_gds_init()