Lines Matching refs:RREG32
74 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR) in r100_is_in_vblank()
79 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR) in r100_is_in_vblank()
91 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
92 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
94 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
95 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
119 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN)) in r100_wait_for_vblank()
122 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN)) in r100_wait_for_vblank()
168 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) in r100_page_flip()
194 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & in r100_page_flip_pending()
354 tmp = RREG32(voltage->gpio.reg); in r100_pm_misc()
363 tmp = RREG32(voltage->gpio.reg); in r100_pm_misc()
455 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); in r100_pm_prepare()
459 tmp = RREG32(RADEON_CRTC_GEN_CNTL); in r100_pm_prepare()
486 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); in r100_pm_finish()
490 tmp = RREG32(RADEON_CRTC_GEN_CNTL); in r100_pm_finish()
508 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE) in r100_gui_idle()
530 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) in r100_hpd_sense()
534 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) in r100_hpd_sense()
559 tmp = RREG32(RADEON_FP_GEN_CNTL); in r100_hpd_set_polarity()
567 tmp = RREG32(RADEON_FP2_GEN_CNTL); in r100_hpd_set_polarity()
659 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; in r100_pci_gart_enable()
666 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; in r100_pci_gart_enable()
681 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; in r100_pci_gart_disable()
735 RREG32(RADEON_GEN_INT_CNTL); in r100_irq_set()
747 tmp = RREG32(R_000044_GEN_INT_STATUS); in r100_irq_disable()
753 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); in r100_irq_ack()
816 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; in r100_irq_process()
831 return RREG32(RADEON_CRTC_CRNT_FRAME); in r100_get_vblank_counter()
833 return RREG32(RADEON_CRTC2_CRNT_FRAME); in r100_get_vblank_counter()
967 tmp = RREG32(R_000E40_RBBM_STATUS); in r100_cp_wait_for_idle()
1064 rptr = RREG32(RADEON_CP_RB_RPTR); in r100_gfx_get_rptr()
1072 return RREG32(RADEON_CP_RB_WPTR); in r100_gfx_get_wptr()
1079 (void)RREG32(RADEON_CP_RB_WPTR); in r100_gfx_set_wptr()
2469 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; in r100_rbbm_fifo_wait_for_entry()
2487 tmp = RREG32(RADEON_RBBM_STATUS); in r100_gui_wait_for_idle()
2503 tmp = RREG32(RADEON_MC_STATUS); in r100_mc_wait_for_idle()
2516 rbbm_status = RREG32(R_000E40_RBBM_STATUS); in r100_gpu_is_lockup()
2529 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; in r100_enable_bm()
2538 tmp = RREG32(R_000030_BUS_CNTL); in r100_bm_disable()
2544 tmp = RREG32(RADEON_BUS_CNTL); in r100_bm_disable()
2556 status = RREG32(R_000E40_RBBM_STATUS); in r100_asic_reset()
2561 status = RREG32(R_000E40_RBBM_STATUS); in r100_asic_reset()
2565 tmp = RREG32(RADEON_CP_RB_CNTL); in r100_asic_reset()
2578 RREG32(R_0000F0_RBBM_SOFT_RESET); in r100_asic_reset()
2582 status = RREG32(R_000E40_RBBM_STATUS); in r100_asic_reset()
2586 RREG32(R_0000F0_RBBM_SOFT_RESET); in r100_asic_reset()
2590 status = RREG32(R_000E40_RBBM_STATUS); in r100_asic_reset()
2652 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); in r100_set_common_regs()
2653 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); in r100_set_common_regs()
2654 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); in r100_set_common_regs()
2700 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) in r100_vram_get_type()
2705 tmp = RREG32(RADEON_MEM_CNTL); in r100_vram_get_type()
2716 tmp = RREG32(RADEON_MEM_CNTL); in r100_vram_get_type()
2733 aper_size = RREG32(RADEON_CONFIG_APER_SIZE); in r100_get_accessible_vram()
2761 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) in r100_get_accessible_vram()
2777 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); in r100_vram_init_sizes()
2781 tom = RREG32(RADEON_NB_TOM); in r100_vram_init_sizes()
2786 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); in r100_vram_init_sizes()
2811 temp = RREG32(RADEON_CONFIG_CNTL); in r100_vga_set_state()
2829 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; in r100_mc_init()
2844 (void)RREG32(RADEON_CLOCK_CNTL_DATA); in r100_pll_errata_after_index()
2845 (void)RREG32(RADEON_CRTC_GEN_CNTL); in r100_pll_errata_after_index()
2866 save = RREG32(RADEON_CLOCK_CNTL_INDEX); in r100_pll_errata_after_data()
2869 tmp = RREG32(RADEON_CLOCK_CNTL_DATA); in r100_pll_errata_after_data()
2882 data = RREG32(RADEON_CLOCK_CNTL_DATA); in r100_pll_rreg()
2925 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); in r100_debugfs_rbbm_info()
2926 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); in r100_debugfs_rbbm_info()
2927 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); in r100_debugfs_rbbm_info()
2930 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; in r100_debugfs_rbbm_info()
2932 value = RREG32(RADEON_RBBM_CMDFIFO_DATA); in r100_debugfs_rbbm_info()
2948 rdp = RREG32(RADEON_CP_RB_RPTR); in r100_debugfs_cp_ring_info()
2949 wdp = RREG32(RADEON_CP_RB_WPTR); in r100_debugfs_cp_ring_info()
2951 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); in r100_debugfs_cp_ring_info()
2975 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); in r100_debugfs_cp_csq_fifo()
2976 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); in r100_debugfs_cp_csq_fifo()
2977 csq_stat = RREG32(RADEON_CP_CSQ_STAT); in r100_debugfs_cp_csq_fifo()
2978 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); in r100_debugfs_cp_csq_fifo()
2998 tmp = RREG32(RADEON_CP_CSQ_DATA); in r100_debugfs_cp_csq_fifo()
3004 tmp = RREG32(RADEON_CP_CSQ_DATA); in r100_debugfs_cp_csq_fifo()
3010 tmp = RREG32(RADEON_CP_CSQ_DATA); in r100_debugfs_cp_csq_fifo()
3023 tmp = RREG32(RADEON_CONFIG_MEMSIZE); in r100_debugfs_mc_info()
3025 tmp = RREG32(RADEON_MC_FB_LOCATION); in r100_debugfs_mc_info()
3027 tmp = RREG32(RADEON_BUS_CNTL); in r100_debugfs_mc_info()
3029 tmp = RREG32(RADEON_MC_AGP_LOCATION); in r100_debugfs_mc_info()
3031 tmp = RREG32(RADEON_AGP_BASE); in r100_debugfs_mc_info()
3033 tmp = RREG32(RADEON_HOST_PATH_CNTL); in r100_debugfs_mc_info()
3035 tmp = RREG32(0x01D0); in r100_debugfs_mc_info()
3037 tmp = RREG32(RADEON_AIC_LO_ADDR); in r100_debugfs_mc_info()
3039 tmp = RREG32(RADEON_AIC_HI_ADDR); in r100_debugfs_mc_info()
3041 tmp = RREG32(0x01E4); in r100_debugfs_mc_info()
3241 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); in r100_bandwidth_update()
3287 temp = RREG32(RADEON_MEM_TIMING_CNTL); in r100_bandwidth_update()
3327 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); in r100_bandwidth_update()
3348 temp = RREG32(RADEON_MEM_CNTL); in r100_bandwidth_update()
3352 temp = RREG32(R300_MC_IND_INDEX); in r100_bandwidth_update()
3356 temp = RREG32(R300_MC_IND_DATA); in r100_bandwidth_update()
3359 temp = RREG32(R300_MC_READ_CNTL_AB); in r100_bandwidth_update()
3363 temp = RREG32(R300_MC_READ_CNTL_AB); in r100_bandwidth_update()
3499 temp = RREG32(RADEON_GRPH_BUFFER_CNTL); in r100_bandwidth_update()
3522 temp = RREG32(RS400_DISP1_REG_CNTL); in r100_bandwidth_update()
3528 temp = RREG32(RS400_DMIF_MEM_CNTL1); in r100_bandwidth_update()
3539 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); in r100_bandwidth_update()
3555 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); in r100_bandwidth_update()
3614 temp = RREG32(RS400_DISP2_REQ_CNTL1); in r100_bandwidth_update()
3620 temp = RREG32(RS400_DISP2_REQ_CNTL2); in r100_bandwidth_update()
3634 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); in r100_bandwidth_update()
3668 tmp = RREG32(scratch); in r100_ring_test()
3745 tmp = RREG32(scratch); in r100_ib_test()
3775 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); in r100_mc_stop()
3776 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); in r100_mc_stop()
3777 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); in r100_mc_stop()
3779 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); in r100_mc_stop()
3780 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); in r100_mc_stop()
3793 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); in r100_mc_stop()
3922 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); in r100_startup()
3951 RREG32(R_000E40_RBBM_STATUS), in r100_resume()
3952 RREG32(R_0007C0_CP_STAT)); in r100_resume()
4009 tmp = RREG32(RADEON_CP_CSQ_CNTL); in r100_restore_sanity()
4013 tmp = RREG32(RADEON_CP_RB_CNTL); in r100_restore_sanity()
4017 tmp = RREG32(RADEON_SCRATCH_UMSK); in r100_restore_sanity()
4055 RREG32(R_000E40_RBBM_STATUS), in r100_init()
4056 RREG32(R_0007C0_CP_STAT)); in r100_init()