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Searched refs:PACKET3 (Results 1 – 25 of 25) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dgfx_v7_0.c2078 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v7_0_ring_test_ring()
2128 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_ring_emit_hdp_flush()
2141 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v7_0_ring_emit_vgt_flush()
2145 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v7_0_ring_emit_vgt_flush()
2167 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in gfx_v7_0_ring_emit_fence_gfx()
2179 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in gfx_v7_0_ring_emit_fence_gfx()
2208 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); in gfx_v7_0_ring_emit_fence_compute()
2243 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v7_0_ring_emit_ib_gfx()
2248 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in gfx_v7_0_ring_emit_ib_gfx()
2250 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v7_0_ring_emit_ib_gfx()
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Dgfx_v6_0.c1790 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v6_0_ring_test_ring()
1814 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v6_0_ring_emit_vgt_flush()
1825 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v6_0_ring_emit_fence()
1828 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in gfx_v6_0_ring_emit_fence()
1837 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in gfx_v6_0_ring_emit_fence()
1855 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v6_0_ring_emit_ib()
1860 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in gfx_v6_0_ring_emit_ib()
1862 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v6_0_ring_emit_ib()
1906 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); in gfx_v6_0_ring_test_ib()
2027 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in gfx_v6_0_cp_gfx_start()
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Dgfx_v8_0.c854 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v8_0_ring_test_ring()
902 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v8_0_ring_test_ib()
1269 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_get_csb_buffer()
1272 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); in gfx_v8_0_get_csb_buffer()
1280 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v8_0_get_csb_buffer()
1291 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in gfx_v8_0_get_csb_buffer()
1297 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_get_csb_buffer()
1300 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v8_0_get_csb_buffer()
1674 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); in gfx_v8_0_do_edc_gpr_workarounds()
1680 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); in gfx_v8_0_do_edc_gpr_workarounds()
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Dgfx_v9_0.c307 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v9_0_write_data_to_reg()
321 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v9_0_wait_reg_mem()
359 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v9_0_ring_test_ring()
407 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v9_0_ring_test_ib()
779 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v9_0_get_csb_buffer()
782 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); in gfx_v9_0_get_csb_buffer()
790 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v9_0_get_csb_buffer()
801 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v9_0_get_csb_buffer()
804 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v9_0_get_csb_buffer()
1427 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); in gfx_v9_0_ngg_en()
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Dsi_enums.h149 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
152 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
Dsoc15d.h50 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro
54 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
Dvid.h107 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro
111 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
Dcikd.h225 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro
229 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
Dsid.h1658 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
1662 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
Damdgpu_amdkfd_gfx_v9.c849 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); in invalidate_tlbs_with_kiq()
/Linux-v4.19/drivers/gpu/drm/radeon/
Dni.c1408 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in cayman_fence_ring_emit()
1414 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cayman_fence_ring_emit()
1430 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); in cayman_ring_ib_execute()
1435 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in cayman_ring_ib_execute()
1441 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); in cayman_ring_ib_execute()
1451 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in cayman_ring_ib_execute()
1557 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in cayman_cp_start()
1575 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cayman_cp_start()
1581 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cayman_cp_start()
1585 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in cayman_cp_start()
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Dcik.c3474 radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in cik_ring_test()
3530 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cik_hdp_flush_cp_ring_emit()
3559 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cik_fence_gfx_ring_emit()
3571 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cik_fence_gfx_ring_emit()
3598 radeon_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); in cik_fence_compute_ring_emit()
3629 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); in cik_semaphore_ring_emit()
3635 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in cik_semaphore_ring_emit()
3690 radeon_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); in cik_copy_cpdma()
3737 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in cik_ring_ib_execute()
3740 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in cik_ring_ib_execute()
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Dsi.c3377 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in si_fence_ring_emit()
3380 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in si_fence_ring_emit()
3389 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in si_fence_ring_emit()
3408 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in si_ring_ib_execute()
3411 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in si_ring_ib_execute()
3416 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in si_ring_ib_execute()
3422 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in si_ring_ib_execute()
3429 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in si_ring_ib_execute()
3443 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in si_ring_ib_execute()
3446 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in si_ring_ib_execute()
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Dr600.c2690 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in r600_cp_start()
2835 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_ring_test()
2873 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in r600_fence_ring_emit()
2879 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in r600_fence_ring_emit()
2887 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in r600_fence_ring_emit()
2892 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in r600_fence_ring_emit()
2895 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_fence_ring_emit()
2899 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_fence_ring_emit()
2930 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); in r600_semaphore_ring_emit()
2937 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in r600_semaphore_ring_emit()
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Dr300d.h64 #define PACKET3(op, n) (CP_PACKET3 | \ macro
Devergreen.c2932 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); in evergreen_ring_ib_execute()
2937 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in evergreen_ring_ib_execute()
2943 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); in evergreen_ring_ib_execute()
2950 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); in evergreen_ring_ib_execute()
3004 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in evergreen_cp_start()
3023 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in evergreen_cp_start()
3029 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in evergreen_cp_start()
3033 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in evergreen_cp_start()
Dsid.h1595 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
1599 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
Dcikd.h1691 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro
1695 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
Drv515d.h204 #define PACKET3(op, n) (CP_PACKET3 | \ macro
Drv770d.h988 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
Dnid.h1157 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
Dr100d.h63 #define PACKET3(op, n) (CP_PACKET3 | \ macro
Devergreend.h1543 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
Dr600d.h1587 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
Dr100.c923 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8)); in r100_copy_blit()