1790 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));  in gfx_v6_0_ring_test_ring()
1814 	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));  in gfx_v6_0_ring_emit_vgt_flush()
1825 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));  in gfx_v6_0_ring_emit_fence()
1828 	amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));  in gfx_v6_0_ring_emit_fence()
1837 	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));  in gfx_v6_0_ring_emit_fence()
1855 		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));  in gfx_v6_0_ring_emit_ib()
1860 		header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);  in gfx_v6_0_ring_emit_ib()
1862 		header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);  in gfx_v6_0_ring_emit_ib()
1906 	ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);  in gfx_v6_0_ring_test_ib()
2027 	amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));  in gfx_v6_0_cp_gfx_start()
2035 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));  in gfx_v6_0_cp_gfx_start()
2049 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v6_0_cp_gfx_start()
2056 						  PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));  in gfx_v6_0_cp_gfx_start()
2064 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v6_0_cp_gfx_start()
2067 	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));  in gfx_v6_0_cp_gfx_start()
2070 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));  in gfx_v6_0_cp_gfx_start()
2309 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));  in gfx_v6_0_ring_emit_pipeline_sync()
2321 		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));  in gfx_v6_0_ring_emit_pipeline_sync()
2323 		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));  in gfx_v6_0_ring_emit_pipeline_sync()
2336 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));  in gfx_v6_0_ring_emit_vm_flush()
2347 		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));  in gfx_v6_0_ring_emit_vm_flush()
2351 		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));  in gfx_v6_0_ring_emit_vm_flush()
2353 		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));  in gfx_v6_0_ring_emit_vm_flush()
2363 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));  in gfx_v6_0_ring_emit_wreg()
2909 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v6_0_get_csb_buffer()
2911 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));  in gfx_v6_0_get_csb_buffer()
2919 					cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));  in gfx_v6_0_get_csb_buffer()
2929 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));  in gfx_v6_0_get_csb_buffer()
2933 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v6_0_get_csb_buffer()
2936 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));  in gfx_v6_0_get_csb_buffer()
3000 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));  in gfx_v6_ring_emit_cntxcntl()