854 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));  in gfx_v8_0_ring_test_ring()
902 	ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);  in gfx_v8_0_ring_test_ib()
1269 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v8_0_get_csb_buffer()
1272 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));  in gfx_v8_0_get_csb_buffer()
1280 					cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));  in gfx_v8_0_get_csb_buffer()
1291 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));  in gfx_v8_0_get_csb_buffer()
1297 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v8_0_get_csb_buffer()
1300 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));  in gfx_v8_0_get_csb_buffer()
1674 		ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);  in gfx_v8_0_do_edc_gpr_workarounds()
1680 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);  in gfx_v8_0_do_edc_gpr_workarounds()
1686 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);  in gfx_v8_0_do_edc_gpr_workarounds()
1694 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);  in gfx_v8_0_do_edc_gpr_workarounds()
1700 		ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);  in gfx_v8_0_do_edc_gpr_workarounds()
1706 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);  in gfx_v8_0_do_edc_gpr_workarounds()
1712 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);  in gfx_v8_0_do_edc_gpr_workarounds()
1720 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);  in gfx_v8_0_do_edc_gpr_workarounds()
1726 		ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);  in gfx_v8_0_do_edc_gpr_workarounds()
1732 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);  in gfx_v8_0_do_edc_gpr_workarounds()
1738 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);  in gfx_v8_0_do_edc_gpr_workarounds()
1746 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);  in gfx_v8_0_do_edc_gpr_workarounds()
4394 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v8_0_cp_gfx_start()
4397 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));  in gfx_v8_0_cp_gfx_start()
4405 				       PACKET3(PACKET3_SET_CONTEXT_REG,  in gfx_v8_0_cp_gfx_start()
4415 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));  in gfx_v8_0_cp_gfx_start()
4420 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v8_0_cp_gfx_start()
4423 	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));  in gfx_v8_0_cp_gfx_start()
4427 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));  in gfx_v8_0_cp_gfx_start()
4640 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));  in gfx_v8_0_kiq_kcq_enable()
4654 		amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));  in gfx_v8_0_kiq_kcq_enable()
4669 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));  in gfx_v8_0_kiq_kcq_enable()
5114 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));  in gfx_v8_0_kcq_disable()
5125 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));  in gfx_v8_0_kcq_disable()
5455 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));  in gfx_v8_0_ring_emit_gds_switch()
5463 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));  in gfx_v8_0_ring_emit_gds_switch()
5471 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));  in gfx_v8_0_ring_emit_gds_switch()
5479 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));  in gfx_v8_0_ring_emit_gds_switch()
6334 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));  in gfx_v8_0_ring_emit_hdp_flush()
6347 	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));  in gfx_v8_0_ring_emit_vgt_flush()
6351 	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));  in gfx_v8_0_ring_emit_vgt_flush()
6363 		header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);  in gfx_v8_0_ring_emit_ib_gfx()
6365 		header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);  in gfx_v8_0_ring_emit_ib_gfx()
6392 	amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));  in gfx_v8_0_ring_emit_ib_compute()
6409 	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));  in gfx_v8_0_ring_emit_fence_gfx()
6429 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));  in gfx_v8_0_ring_emit_pipeline_sync()
6448 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));  in gfx_v8_0_ring_emit_vm_flush()
6461 		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));  in gfx_v8_0_ring_emit_vm_flush()
6586 	amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));  in gfx_v8_0_ring_emit_fence_compute()
6606 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));  in gfx_v8_0_ring_emit_fence_kiq()
6615 		amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));  in gfx_v8_0_ring_emit_fence_kiq()
6626 	amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));  in gfx_v8_ring_emit_sb()
6658 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));  in gfx_v8_ring_emit_cntxcntl()
6667 	amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));  in gfx_v8_0_ring_emit_init_cond_exec()
6694 	amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));  in gfx_v8_0_ring_emit_rreg()
6723 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));  in gfx_v8_0_ring_emit_wreg()
7148 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
7192 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
7222 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
7461 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt_ce));  in gfx_v8_0_ring_emit_ce_meta()
7494 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt_de));  in gfx_v8_0_ring_emit_de_meta()