| /Linux-v4.19/drivers/mtd/nand/raw/ |
| D | Kconfig | 5 bool "NAND ECC Smart Media byte order"
14 tristate "Raw/Parallel NAND Device Support"
19 NAND flash devices. For further information see
36 ECC codes. They are used with NAND devices requiring more than 1 bit
47 tristate "Support Denali NAND controller on Intel Moorestown"
51 Enable the driver for NAND flash on Intel Moorestown, using the
52 Denali NAND controller core.
55 tristate "Support Denali NAND controller as a DT device"
59 Enable the driver for NAND flash on platforms using a Denali NAND
63 tristate "GPIO assisted NAND Flash driver"
[all …]
|
| /Linux-v4.19/Documentation/devicetree/bindings/mtd/ |
| D | nand.txt | 1 * NAND chip and NAND controller generic binding
3 NAND controller/NAND chip representation:
5 The NAND controller should be represented with its own DT node, and all
6 NAND chips attached to this controller should be defined as children nodes
7 of the NAND controller. This representation should be enforced even for
10 Mandatory NAND controller properties:
16 Optional NAND controller properties
20 Optional NAND chip properties:
22 - nand-ecc-mode : String, operation mode of the NAND ecc mode.
27 - nand-ecc-algo: string, algorithm of NAND ECC.
[all …]
|
| D | ingenic,jz4780-nand.txt | 1 * Ingenic JZ4780 NAND/BCH
3 This file documents the device tree bindings for NAND flash devices on the
4 JZ4780. NAND devices are connected to the NEMC controller (described in
5 memory-controllers/ingenic,jz4780-nemc.txt), and thus NAND device nodes must
8 Required NAND controller device properties:
10 - reg: For each bank with a NAND chip attached, should specify a bank number,
13 Optional NAND controller device properties:
20 - Individual NAND chips are children of the NAND controller node.
28 - nand-ecc-mode: String, operation mode of the NAND ecc mode. "hw" by default
33 Optional child node of NAND chip nodes:
[all …]
|
| D | oxnas-nand.txt | 1 * Oxford Semiconductor OXNAS NAND Controller
3 Please refer to nand.txt for generic information regarding MTD NAND bindings.
7 - reg: Base address and length for NAND mapped memory.
10 - clocks: phandle to the NAND gate clock if needed.
11 - resets: phandle to the NAND reset control if needed.
|
| D | mtk-nand.txt | 1 MTK SoCs NAND FLASH controller (NFC) DT binding
3 This file documents the device tree bindings for MTK SoCs NAND controllers.
10 1) NFC NAND Controller Interface (NFI):
13 The first part of NFC is NAND Controller Interface (NFI) HW.
24 - #address-cells: NAND chip index, should be 1.
42 - children nodes: NAND chips.
48 - nand-on-flash-bbt: Store BBT on NAND Flash.
49 - nand-ecc-mode: the NAND ecc mode (check driver for supported modes)
74 According to MTK NAND controller design,
76 that MTK NAND controller supports.
[all …]
|
| D | brcm,brcmnand.txt | 1 * Broadcom STB NAND Controller
3 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
19 the core NAND controller, of the following form:
32 - reg : the register start and length for NAND register region.
34 (optional) NAND flash cache range (if at non-standard offset)
38 - interrupts : The NAND CTLRDY interrupt and (if Flash DMA is available)
42 May be "nand", if the SoC has the individual NAND
49 - clock : reference to the clock for the NAND controller
56 -- Additional SoC-specific NAND controller properties --
58 The NAND controller is integrated differently on the variety of SoCs on which it
[all …]
|
| D | qcom_nandc.txt | 1 * Qualcomm NAND controller
5 * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x
7 * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
9 * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
20 NAND. Refer to dma.txt and qcom_adm.txt for more details
23 number specified for the NAND controller on the given
26 number specified for the NAND controller on the given
31 and the channel number to be used for NAND. Refer to
37 * NAND chip-select
40 chip-selects which (may) contain NAND flash chips. Their properties are as
|
| D | atmel-nand.txt | 1 Atmel NAND flash controller bindings
3 The NAND flash controller node should be defined under the EBI bus (see
5 One or several NAND devices can be defined under this NAND controller.
6 The NAND controller might be connected to an ECC engine.
8 * NAND controller bindings:
29 * NAND device/chip bindings:
32 - reg: describes the CS lines assigned to the NAND device. If the NAND device
35 1st entry: the CS line this NAND chip is connected to
41 - rb-gpios: the GPIO(s) used to check the Ready/Busy status of the NAND.
48 Documentation/devicetree/bindings/mtd/{common,nand}.txt also apply to the NAND
[all …]
|
| D | nvidia-tegra20-nand.txt | 1 NVIDIA Tegra NAND Flash controller
18 Individual NAND chips are children of the NAND controller node. Currently
19 only one NAND chip supported.
25 - nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
27 - nand-ecc-algo: string, algorithm of NAND ECC.
41 Optional child node of NAND chip nodes:
|
| D | fsmc-nand.txt | 2 NAND Interface
13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
27 NAND flash in response to SMWAITn. Zero means 1 cycle,
32 - bank: default NAND bank to use (0-3 are valid, 0 is the default).
47 0xd2000000 0x0010 /* NAND Base DATA */
48 0xd2020000 0x0010 /* NAND Base ADDR */
49 0xd2010000 0x0010>; /* NAND Base CMD */
|
| D | gpio-control-nand.txt | 1 GPIO assisted NAND flash
3 The GPIO assisted NAND flash uses a memory mapped interface to
4 read/write the NAND commands and data and GPIO pins for the control
10 resource describes the data bus connected to the NAND flash and all accesses
14 - gpios : Specifies the GPIO pins to control the NAND device. The order of
24 the GPIO's and the NAND flash data bus. If present, then after changing
|
| D | marvell-nand.txt | 1 Marvell NAND Flash Controller (NFC)
13 - reg: NAND flash controller memory area.
14 - #address-cells: shall be set to 1. Encode the NAND CS.
16 - interrupts: shall define the NAND controller interrupt.
17 - clocks: shall reference the NAND controller clocks, the second one is
22 NAND controller related registers (only required with the
27 - dmas: shall reference DMA channel associated to the NAND controller.
35 Children nodes represent the available NAND chips.
52 the NAND chip. This value may be overwritten with nand-ecc-strength
55 - nand-ecc-step-size: see nand.txt. Marvell's NAND flash controller does
|
| D | vf610-nfc.txt | 1 Freescale's NAND flash controller (NFC)
3 This variant of the Freescale NAND flash controller (NFC) can be found on
13 - assigned-clock-rates: The NAND bus timing is derived from this clock
14 rate and should not exceed maximum timing for any NAND memory chip
15 in a board stuffing. Typical NAND memory timings derived from this
24 only handle one NAND chip.
|
| D | davinci-nand.txt | 1 Device tree bindings for Texas instruments Davinci/Keystone NAND controller
4 NAND interface contains.
29 address for the chip select space the NAND Flash
35 address for the chip select space the NAND Flash
42 - nand-ecc-mode: operation mode of the NAND ecc mode. ECC mode
58 - ti,davinci-ecc-mode: operation mode of the NAND ecc mode. ECC mode
71 the address space. See partition.txt for more detail. The NAND Flash timing
|
| D | lpc32xx-mlc.txt | 1 NXP LPC32xx SoC NAND MLC controller
6 - interrupts: The NAND interrupt specification
7 - gpios: GPIO specification for NAND write protect
10 User Manual 7.5.14 MLC NAND Timing Register (the values here are specified in
|
| D | spi-nand.txt | 1 SPI NAND flash
5 - reg: should encode the chip-select line used to access the NAND chip
|
| /Linux-v4.19/drivers/pinctrl/tegra/ |
| D | pinctrl-tegra30.c | 2205 …PINGROUP(gmi_wp_n_pc7, RSVD1, NAND, GMI, GMI_ALT, 0x31c0, N, …
2230 …PINGROUP(gmi_ad0_pg0, RSVD1, NAND, GMI, RSVD4, 0x31f0, N, …
2231 …PINGROUP(gmi_ad1_pg1, RSVD1, NAND, GMI, RSVD4, 0x31f4, N, …
2232 …PINGROUP(gmi_ad2_pg2, RSVD1, NAND, GMI, RSVD4, 0x31f8, N, …
2233 …PINGROUP(gmi_ad3_pg3, RSVD1, NAND, GMI, RSVD4, 0x31fc, N, …
2234 …PINGROUP(gmi_ad4_pg4, RSVD1, NAND, GMI, RSVD4, 0x3200, N, …
2235 …PINGROUP(gmi_ad5_pg5, RSVD1, NAND, GMI, RSVD4, 0x3204, N, …
2236 …PINGROUP(gmi_ad6_pg6, RSVD1, NAND, GMI, RSVD4, 0x3208, N, …
2237 …PINGROUP(gmi_ad7_pg7, RSVD1, NAND, GMI, RSVD4, 0x320c, N, …
2238 …PINGROUP(gmi_ad8_ph0, PWM0, NAND, GMI, RSVD4, 0x3210, N, …
[all …]
|
| D | pinctrl-tegra114.c | 1673 …PINGROUP(gmi_wp_n_pc7, RSVD1, NAND, GMI, GMI_ALT, 0x31c0, N, N…
1675 …PINGROUP(gmi_wait_pi7, SPI4, NAND, GMI, DTV, 0x31c8, N, N…
1676 …PINGROUP(gmi_adv_n_pk0, RSVD1, NAND, GMI, TRACE, 0x31cc, N, N…
1677 …PINGROUP(gmi_clk_pk1, SDMMC2, NAND, GMI, TRACE, 0x31d0, N, N…
1678 …PINGROUP(gmi_cs0_n_pj0, RSVD1, NAND, GMI, USB, 0x31d4, N, N…
1679 …PINGROUP(gmi_cs1_n_pj2, RSVD1, NAND, GMI, SOC, 0x31d8, N, N…
1680 …PINGROUP(gmi_cs2_n_pk3, SDMMC2, NAND, GMI, TRACE, 0x31dc, N, N…
1681 …PINGROUP(gmi_cs3_n_pk4, SDMMC2, NAND, GMI, GMI_ALT, 0x31e0, N, N…
1682 …PINGROUP(gmi_cs4_n_pk2, USB, NAND, GMI, TRACE, 0x31e4, N, N…
1683 …PINGROUP(gmi_cs6_n_pi3, NAND, NAND_ALT, GMI, SPI4, 0x31e8, N, N…
[all …]
|
| /Linux-v4.19/Documentation/arm/Samsung-S3C24XX/ |
| D | NAND.txt | 1 S3C24XX NAND Support
7 Small Page NAND
14 Large Page NAND
17 The driver is capable of handling NAND flash with a 2KiB page
|
| /Linux-v4.19/drivers/staging/mt29f_spinand/ |
| D | Kconfig | 5 This enables support for accessing Micron SPI NAND flash
7 If you have Micron SPI NAND chip say yes.
16 Enables Hardware ECC support for Micron SPI NAND.
|
| /Linux-v4.19/arch/powerpc/boot/dts/fsl/ |
| D | p1010rdb-pa.dtsi | 40 label = "NAND U-Boot Image";
47 label = "NAND DTB Image";
53 label = "NAND Linux Kernel Image";
59 label = "NAND Compressed RFS Image";
65 label = "NAND JFFS2 Root File System";
71 label = "NAND User area";
|
| D | p2020rdb.dts | 35 /* NOR and NAND Flashes */
97 label = "NAND (RO) U-Boot Image";
104 label = "NAND (RO) DTB Image";
111 label = "NAND (RO) Linux Kernel Image";
118 label = "NAND (RO) Compressed RFS Image";
125 label = "NAND (RW) JFFS2 Root File System";
131 label = "NAND (RW) Writable User area";
|
| /Linux-v4.19/arch/arm/boot/dts/ |
| D | dra7-evm.dts | 411 * support NAND on dra7-evm. Keep it disabled. Enabling it
450 * NAND flash this is equal to size of erase-block */
454 label = "NAND.SPL";
458 label = "NAND.SPL.backup1";
462 label = "NAND.SPL.backup2";
466 label = "NAND.SPL.backup3";
470 label = "NAND.u-boot-spl-os";
474 label = "NAND.u-boot";
478 label = "NAND.u-boot-env";
482 label = "NAND.u-boot-env.backup1";
[all …]
|
| D | dra72-evm-common.dtsi | 290 * support NAND on dra72-evm. Keep it disabled. Enabling it
296 /* To use NAND, DIP switch SW5 must be set like so:
333 * NAND flash this is equal to size of erase-block */
337 label = "NAND.SPL";
341 label = "NAND.SPL.backup1";
345 label = "NAND.SPL.backup2";
349 label = "NAND.SPL.backup3";
353 label = "NAND.u-boot-spl-os";
357 label = "NAND.u-boot";
361 label = "NAND.u-boot-env";
[all …]
|
| /Linux-v4.19/drivers/mtd/nand/spi/ |
| D | Kconfig | 2 tristate "SPI NAND device Support"
7 This is the framework for the SPI NAND device drivers.
|
