1* Ingenic JZ4780 NAND/BCH
2
3This file documents the device tree bindings for NAND flash devices on the
4JZ4780. NAND devices are connected to the NEMC controller (described in
5memory-controllers/ingenic,jz4780-nemc.txt), and thus NAND device nodes must
6be children of the NEMC node.
7
8Required NAND controller device properties:
9- compatible: Should be set to "ingenic,jz4780-nand".
10- reg: For each bank with a NAND chip attached, should specify a bank number,
11  an offset of 0 and a size of 0x1000000 (i.e. the whole NEMC bank).
12
13Optional NAND controller device properties:
14- ingenic,bch-controller: To make use of the hardware BCH controller, this
15  property must contain a phandle for the BCH controller node. The required
16  properties for this node are described below. If this is not specified,
17  software BCH will be used instead.
18
19Optional children nodes:
20- Individual NAND chips are children of the NAND controller node.
21
22Required children node properties:
23- reg: An integer ranging from 1 to 6 representing the CS line to use.
24
25Optional children node properties:
26- nand-ecc-step-size: ECC block size in bytes.
27- nand-ecc-strength: ECC strength (max number of correctable bits).
28- nand-ecc-mode: String, operation mode of the NAND ecc mode. "hw" by default
29- nand-on-flash-bbt: boolean to enable on flash bbt option, if not present false
30- rb-gpios: GPIO specifier for the busy pin.
31- wp-gpios: GPIO specifier for the write protect pin.
32
33Optional child node of NAND chip nodes:
34- partitions: see Documentation/devicetree/bindings/mtd/partition.txt
35
36Example:
37
38nemc: nemc@13410000 {
39	...
40
41	nandc: nand-controller@1 {
42		compatible = "ingenic,jz4780-nand";
43		reg = <1 0 0x1000000>;	/* Bank 1 */
44
45		#address-cells = <1>;
46		#size-cells = <0>;
47
48		ingenic,bch-controller = <&bch>;
49
50		nand@1 {
51			reg = <1>;
52
53			nand-ecc-step-size = <1024>;
54			nand-ecc-strength = <24>;
55			nand-ecc-mode = "hw";
56			nand-on-flash-bbt;
57
58			rb-gpios = <&gpa 20 GPIO_ACTIVE_LOW>;
59			wp-gpios = <&gpf 22 GPIO_ACTIVE_LOW>;
60
61			partitions {
62				#address-cells = <2>;
63				#size-cells = <2>;
64				...
65			}
66		};
67	};
68};
69
70The BCH controller is a separate SoC component used for error correction on
71NAND devices. The following is a description of the device properties for a
72BCH controller.
73
74Required BCH properties:
75- compatible: Should be set to "ingenic,jz4780-bch".
76- reg: Should specify the BCH controller registers location and length.
77- clocks: Clock for the BCH controller.
78
79Example:
80
81bch: bch@134d0000 {
82	compatible = "ingenic,jz4780-bch";
83	reg = <0x134d0000 0x10000>;
84
85	clocks = <&cgu JZ4780_CLK_BCH>;
86};
87