Lines Matching refs:NAND
1 * Broadcom STB NAND Controller
3 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
19 the core NAND controller, of the following form:
32 - reg : the register start and length for NAND register region.
34 (optional) NAND flash cache range (if at non-standard offset)
38 - interrupts : The NAND CTLRDY interrupt and (if Flash DMA is available)
42 May be "nand", if the SoC has the individual NAND
49 - clock : reference to the clock for the NAND controller
56 -- Additional SoC-specific NAND controller properties --
58 The NAND controller is integrated differently on the variety of SoCs on which it
60 with which to control the 8 exposed NAND interrupts, as well as hardware for
64 ways, sometimes with registers that lump multiple NAND-related functions
67 we define additional 'compatible' properties and associated register resources within the NAND cont…
92 * NAND chip-select
95 to represent enabled chip-selects which (may) contain NAND flash chips. Their
116 the flash geometry (particularly the NAND page
118 from NAND, the boot controller has only a limited