1/* 2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8/dts-v1/; 9 10#include "dra74x.dtsi" 11#include "dra7-evm-common.dtsi" 12#include "dra74x-mmc-iodelay.dtsi" 13 14/ { 15 model = "TI DRA742"; 16 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"; 17 18 memory@0 { 19 device_type = "memory"; 20 reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */ 21 }; 22 23 evm_12v0: fixedregulator-evm_12v0 { 24 /* main supply */ 25 compatible = "regulator-fixed"; 26 regulator-name = "evm_12v0"; 27 regulator-min-microvolt = <12000000>; 28 regulator-max-microvolt = <12000000>; 29 regulator-always-on; 30 regulator-boot-on; 31 }; 32 33 evm_1v8_sw: fixedregulator-evm_1v8 { 34 compatible = "regulator-fixed"; 35 regulator-name = "evm_1v8"; 36 vin-supply = <&smps9_reg>; 37 regulator-min-microvolt = <1800000>; 38 regulator-max-microvolt = <1800000>; 39 }; 40 41 evm_3v3_sd: fixedregulator-sd { 42 compatible = "regulator-fixed"; 43 regulator-name = "evm_3v3_sd"; 44 regulator-min-microvolt = <3300000>; 45 regulator-max-microvolt = <3300000>; 46 enable-active-high; 47 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; 48 }; 49 50 evm_3v3_sw: fixedregulator-evm_3v3_sw { 51 compatible = "regulator-fixed"; 52 regulator-name = "evm_3v3_sw"; 53 vin-supply = <&sysen1>; 54 regulator-min-microvolt = <3300000>; 55 regulator-max-microvolt = <3300000>; 56 }; 57 58 aic_dvdd: fixedregulator-aic_dvdd { 59 /* TPS77018DBVT */ 60 compatible = "regulator-fixed"; 61 regulator-name = "aic_dvdd"; 62 vin-supply = <&evm_3v3_sw>; 63 regulator-min-microvolt = <1800000>; 64 regulator-max-microvolt = <1800000>; 65 }; 66 67 evm_3v3: fixedregulator-evm3v3 { 68 /* Output of Cntlr A of TPS43351-Q1 on dra7-evm */ 69 compatible = "regulator-fixed"; 70 regulator-name = "evm_3v3"; 71 regulator-min-microvolt = <3300000>; 72 regulator-max-microvolt = <3300000>; 73 vin-supply = <&evm_12v0>; 74 regulator-always-on; 75 regulator-boot-on; 76 }; 77 78 evm_5v0: fixedregulator-evm_5v0 { 79 /* Output of Cntlr B of TPS43351-Q1 on dra7-evm */ 80 compatible = "regulator-fixed"; 81 regulator-name = "evm_5v0"; 82 regulator-min-microvolt = <5000000>; 83 regulator-max-microvolt = <5000000>; 84 vin-supply = <&evm_12v0>; 85 regulator-always-on; 86 regulator-boot-on; 87 }; 88 89 evm_3v6: fixedregulator-evm_3v6 { 90 compatible = "regulator-fixed"; 91 regulator-name = "evm_3v6"; 92 regulator-min-microvolt = <3600000>; 93 regulator-max-microvolt = <3600000>; 94 vin-supply = <&evm_5v0>; 95 regulator-always-on; 96 regulator-boot-on; 97 }; 98 99 vmmcwl_fixed: fixedregulator-mmcwl { 100 compatible = "regulator-fixed"; 101 regulator-name = "vmmcwl_fixed"; 102 regulator-min-microvolt = <1800000>; 103 regulator-max-microvolt = <1800000>; 104 gpio = <&gpio5 8 0>; 105 startup-delay-us = <70000>; 106 enable-active-high; 107 }; 108 109 vtt_fixed: fixedregulator-vtt { 110 compatible = "regulator-fixed"; 111 regulator-name = "vtt_fixed"; 112 regulator-min-microvolt = <1350000>; 113 regulator-max-microvolt = <1350000>; 114 regulator-always-on; 115 regulator-boot-on; 116 enable-active-high; 117 vin-supply = <&sysen2>; 118 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; 119 }; 120 121}; 122 123&dra7_pmx_core { 124 dcan1_pins_default: dcan1_pins_default { 125 pinctrl-single,pins = < 126 DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ 127 DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ 128 >; 129 }; 130 131 dcan1_pins_sleep: dcan1_pins_sleep { 132 pinctrl-single,pins = < 133 DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ 134 DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ 135 >; 136 }; 137}; 138 139&i2c1 { 140 status = "okay"; 141 clock-frequency = <400000>; 142 143 tps659038: tps659038@58 { 144 compatible = "ti,tps659038"; 145 reg = <0x58>; 146 ti,palmas-override-powerhold; 147 ti,system-power-controller; 148 149 tps659038_pmic { 150 compatible = "ti,tps659038-pmic"; 151 152 regulators { 153 smps123_reg: smps123 { 154 /* VDD_MPU */ 155 regulator-name = "smps123"; 156 regulator-min-microvolt = < 850000>; 157 regulator-max-microvolt = <1250000>; 158 regulator-always-on; 159 regulator-boot-on; 160 }; 161 162 smps45_reg: smps45 { 163 /* VDD_DSPEVE */ 164 regulator-name = "smps45"; 165 regulator-min-microvolt = < 850000>; 166 regulator-max-microvolt = <1250000>; 167 regulator-always-on; 168 regulator-boot-on; 169 }; 170 171 smps6_reg: smps6 { 172 /* VDD_GPU - over VDD_SMPS6 */ 173 regulator-name = "smps6"; 174 regulator-min-microvolt = <850000>; 175 regulator-max-microvolt = <1250000>; 176 regulator-always-on; 177 regulator-boot-on; 178 }; 179 180 smps7_reg: smps7 { 181 /* CORE_VDD */ 182 regulator-name = "smps7"; 183 regulator-min-microvolt = <850000>; 184 regulator-max-microvolt = <1150000>; 185 regulator-always-on; 186 regulator-boot-on; 187 }; 188 189 smps8_reg: smps8 { 190 /* VDD_IVAHD */ 191 regulator-name = "smps8"; 192 regulator-min-microvolt = < 850000>; 193 regulator-max-microvolt = <1250000>; 194 regulator-always-on; 195 regulator-boot-on; 196 }; 197 198 smps9_reg: smps9 { 199 /* VDDS1V8 */ 200 regulator-name = "smps9"; 201 regulator-min-microvolt = <1800000>; 202 regulator-max-microvolt = <1800000>; 203 regulator-always-on; 204 regulator-boot-on; 205 }; 206 207 ldo1_reg: ldo1 { 208 /* LDO1_OUT --> SDIO */ 209 regulator-name = "ldo1"; 210 regulator-min-microvolt = <1800000>; 211 regulator-max-microvolt = <3300000>; 212 regulator-always-on; 213 regulator-boot-on; 214 }; 215 216 ldo2_reg: ldo2 { 217 /* VDD_RTCIO */ 218 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */ 219 regulator-name = "ldo2"; 220 regulator-min-microvolt = <3300000>; 221 regulator-max-microvolt = <3300000>; 222 regulator-always-on; 223 regulator-boot-on; 224 }; 225 226 ldo3_reg: ldo3 { 227 /* VDDA_1V8_PHY */ 228 regulator-name = "ldo3"; 229 regulator-min-microvolt = <1800000>; 230 regulator-max-microvolt = <1800000>; 231 regulator-always-on; 232 regulator-boot-on; 233 }; 234 235 ldo9_reg: ldo9 { 236 /* VDD_RTC */ 237 regulator-name = "ldo9"; 238 regulator-min-microvolt = <1050000>; 239 regulator-max-microvolt = <1050000>; 240 regulator-always-on; 241 regulator-boot-on; 242 regulator-allow-bypass; 243 }; 244 245 ldoln_reg: ldoln { 246 /* VDDA_1V8_PLL */ 247 regulator-name = "ldoln"; 248 regulator-min-microvolt = <1800000>; 249 regulator-max-microvolt = <1800000>; 250 regulator-always-on; 251 regulator-boot-on; 252 }; 253 254 ldousb_reg: ldousb { 255 /* VDDA_3V_USB: VDDA_USBHS33 */ 256 regulator-name = "ldousb"; 257 regulator-min-microvolt = <3300000>; 258 regulator-max-microvolt = <3300000>; 259 regulator-boot-on; 260 }; 261 262 /* REGEN1 is unused */ 263 264 regen2: regen2 { 265 /* Needed for PMIC internal resources */ 266 regulator-name = "regen2"; 267 regulator-boot-on; 268 regulator-always-on; 269 }; 270 271 /* REGEN3 is unused */ 272 273 sysen1: sysen1 { 274 /* PMIC_REGEN_3V3 */ 275 regulator-name = "sysen1"; 276 regulator-boot-on; 277 regulator-always-on; 278 }; 279 280 sysen2: sysen2 { 281 /* PMIC_REGEN_DDR */ 282 regulator-name = "sysen2"; 283 regulator-boot-on; 284 regulator-always-on; 285 }; 286 }; 287 }; 288 }; 289 290 pcf_lcd: gpio@20 { 291 compatible = "ti,pcf8575", "nxp,pcf8575"; 292 reg = <0x20>; 293 gpio-controller; 294 #gpio-cells = <2>; 295 interrupt-parent = <&gpio6>; 296 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 297 interrupt-controller; 298 #interrupt-cells = <2>; 299 }; 300 301 pcf_gpio_21: gpio@21 { 302 compatible = "ti,pcf8575", "nxp,pcf8575"; 303 reg = <0x21>; 304 lines-initial-states = <0x1408>; 305 gpio-controller; 306 #gpio-cells = <2>; 307 interrupt-parent = <&gpio6>; 308 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 309 interrupt-controller; 310 #interrupt-cells = <2>; 311 }; 312 313 tlv320aic3106: tlv320aic3106@19 { 314 #sound-dai-cells = <0>; 315 compatible = "ti,tlv320aic3106"; 316 reg = <0x19>; 317 adc-settle-ms = <40>; 318 ai3x-micbias-vg = <1>; /* 2.0V */ 319 status = "okay"; 320 321 /* Regulators */ 322 AVDD-supply = <&evm_3v3_sw>; 323 IOVDD-supply = <&evm_3v3_sw>; 324 DRVDD-supply = <&evm_3v3_sw>; 325 DVDD-supply = <&aic_dvdd>; 326 }; 327}; 328 329&i2c2 { 330 status = "okay"; 331 clock-frequency = <400000>; 332 333 pcf_hdmi: gpio@26 { 334 compatible = "ti,pcf8575", "nxp,pcf8575"; 335 reg = <0x26>; 336 gpio-controller; 337 #gpio-cells = <2>; 338 p1 { 339 /* vin6_sel_s0: high: VIN6, low: audio */ 340 gpio-hog; 341 gpios = <1 GPIO_ACTIVE_HIGH>; 342 output-low; 343 line-name = "vin6_sel_s0"; 344 }; 345 }; 346}; 347 348&mmc1 { 349 status = "okay"; 350 vmmc-supply = <&evm_3v3_sd>; 351 vqmmc-supply = <&ldo1_reg>; 352 bus-width = <4>; 353 /* 354 * SDCD signal is not being used here - using the fact that GPIO mode 355 * is always hardwired. 356 */ 357 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; 358 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104"; 359 pinctrl-0 = <&mmc1_pins_default>; 360 pinctrl-1 = <&mmc1_pins_hs>; 361 pinctrl-2 = <&mmc1_pins_sdr12>; 362 pinctrl-3 = <&mmc1_pins_sdr25>; 363 pinctrl-4 = <&mmc1_pins_sdr50>; 364 pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>; 365 pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>; 366 pinctrl-7 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>; 367 pinctrl-8 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; 368}; 369 370&mmc2 { 371 status = "okay"; 372 vmmc-supply = <&evm_1v8_sw>; 373 vqmmc-supply = <&evm_1v8_sw>; 374 bus-width = <8>; 375 non-removable; 376 pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v"; 377 pinctrl-0 = <&mmc2_pins_default>; 378 pinctrl-1 = <&mmc2_pins_hs>; 379 pinctrl-2 = <&mmc2_pins_ddr_1_8v_rev11 &mmc2_iodelay_ddr_1_8v_rev11_conf>; 380 pinctrl-3 = <&mmc2_pins_ddr_rev20>; 381 pinctrl-4 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev11_conf>; 382 pinctrl-5 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>; 383}; 384 385&mmc4 { 386 status = "okay"; 387 vmmc-supply = <&evm_3v6>; 388 vqmmc-supply = <&vmmcwl_fixed>; 389 pinctrl-names = "default-rev11", "default", "hs-rev11", "hs", "sdr12-rev11", "sdr12", "sdr25-rev11", "sdr25"; 390 pinctrl-0 = <&mmc4_pins_default &mmc4_iodelay_ds_rev11_conf>; 391 pinctrl-1 = <&mmc4_pins_default &mmc4_iodelay_ds_rev20_conf>; 392 pinctrl-2 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>; 393 pinctrl-3 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>; 394 pinctrl-4 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>; 395 pinctrl-5 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>; 396 pinctrl-6 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>; 397 pinctrl-7 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>; 398}; 399 400&cpu0 { 401 vdd-supply = <&smps123_reg>; 402}; 403 404&elm { 405 status = "okay"; 406}; 407 408&gpmc { 409 /* 410 * For the existing IOdelay configuration via U-Boot we don't 411 * support NAND on dra7-evm. Keep it disabled. Enabling it 412 * requires a different configuration by U-Boot. 413 */ 414 status = "disabled"; 415 ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ 416 nand@0,0 { 417 compatible = "ti,omap2-nand"; 418 reg = <0 0 4>; /* device IO registers */ 419 interrupt-parent = <&gpmc>; 420 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 421 <1 IRQ_TYPE_NONE>; /* termcount */ 422 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ 423 ti,nand-xfer-type = "prefetch-dma"; 424 ti,nand-ecc-opt = "bch8"; 425 ti,elm-id = <&elm>; 426 nand-bus-width = <16>; 427 gpmc,device-width = <2>; 428 gpmc,sync-clk-ps = <0>; 429 gpmc,cs-on-ns = <0>; 430 gpmc,cs-rd-off-ns = <80>; 431 gpmc,cs-wr-off-ns = <80>; 432 gpmc,adv-on-ns = <0>; 433 gpmc,adv-rd-off-ns = <60>; 434 gpmc,adv-wr-off-ns = <60>; 435 gpmc,we-on-ns = <10>; 436 gpmc,we-off-ns = <50>; 437 gpmc,oe-on-ns = <4>; 438 gpmc,oe-off-ns = <40>; 439 gpmc,access-ns = <40>; 440 gpmc,wr-access-ns = <80>; 441 gpmc,rd-cycle-ns = <80>; 442 gpmc,wr-cycle-ns = <80>; 443 gpmc,bus-turnaround-ns = <0>; 444 gpmc,cycle2cycle-delay-ns = <0>; 445 gpmc,clk-activation-ns = <0>; 446 gpmc,wr-data-mux-bus-ns = <0>; 447 /* MTD partition table */ 448 /* All SPL-* partitions are sized to minimal length 449 * which can be independently programmable. For 450 * NAND flash this is equal to size of erase-block */ 451 #address-cells = <1>; 452 #size-cells = <1>; 453 partition@0 { 454 label = "NAND.SPL"; 455 reg = <0x00000000 0x000020000>; 456 }; 457 partition@1 { 458 label = "NAND.SPL.backup1"; 459 reg = <0x00020000 0x00020000>; 460 }; 461 partition@2 { 462 label = "NAND.SPL.backup2"; 463 reg = <0x00040000 0x00020000>; 464 }; 465 partition@3 { 466 label = "NAND.SPL.backup3"; 467 reg = <0x00060000 0x00020000>; 468 }; 469 partition@4 { 470 label = "NAND.u-boot-spl-os"; 471 reg = <0x00080000 0x00040000>; 472 }; 473 partition@5 { 474 label = "NAND.u-boot"; 475 reg = <0x000c0000 0x00100000>; 476 }; 477 partition@6 { 478 label = "NAND.u-boot-env"; 479 reg = <0x001c0000 0x00020000>; 480 }; 481 partition@7 { 482 label = "NAND.u-boot-env.backup1"; 483 reg = <0x001e0000 0x00020000>; 484 }; 485 partition@8 { 486 label = "NAND.kernel"; 487 reg = <0x00200000 0x00800000>; 488 }; 489 partition@9 { 490 label = "NAND.file-system"; 491 reg = <0x00a00000 0x0f600000>; 492 }; 493 }; 494}; 495 496&usb2_phy1 { 497 phy-supply = <&ldousb_reg>; 498}; 499 500&usb2_phy2 { 501 phy-supply = <&ldousb_reg>; 502}; 503 504&gpio7 { 505 ti,no-reset-on-init; 506 ti,no-idle-on-init; 507}; 508 509&mac { 510 status = "okay"; 511 dual_emac; 512}; 513 514&cpsw_emac0 { 515 phy_id = <&davinci_mdio>, <2>; 516 phy-mode = "rgmii"; 517 dual_emac_res_vlan = <1>; 518}; 519 520&cpsw_emac1 { 521 phy_id = <&davinci_mdio>, <3>; 522 phy-mode = "rgmii"; 523 dual_emac_res_vlan = <2>; 524}; 525 526&dcan1 { 527 status = "ok"; 528 pinctrl-names = "default", "sleep", "active"; 529 pinctrl-0 = <&dcan1_pins_sleep>; 530 pinctrl-1 = <&dcan1_pins_sleep>; 531 pinctrl-2 = <&dcan1_pins_default>; 532}; 533
