Searched +full:zynqmp +full:- +full:rtc (Results 1 – 18 of 18) sorted by relevance
/Linux-v6.1/Documentation/devicetree/bindings/rtc/ |
D | xlnx,zynqmp-rtc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/rtc/xlnx,zynqmp-rtc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 RTC controller for the Xilinx Zynq MPSoC Real Time Clock. 11 The RTC controller has separate IRQ lines for seconds and alarm. 14 - Michal Simek <michal.simek@xilinx.com> 17 - $ref: rtc.yaml# 21 const: xlnx,zynqmp-rtc 29 clock-names: [all …]
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/Linux-v6.1/arch/arm64/boot/dts/xilinx/ |
D | zynqmp-zc1751-xm017-dc3.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP zc1751-xm017-dc3 5 * (C) Copyright 2016 - 2021, Xilinx, Inc. 10 /dts-v1/; 12 #include "zynqmp.dtsi" 13 #include "zynqmp-clk-ccf.dtsi" 14 #include <dt-bindings/phy/phy.h> 17 model = "ZynqMP zc1751-xm017-dc3 RevA"; 18 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; 25 rtc0 = &rtc; [all …]
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D | zynqmp-zc1751-xm018-dc4.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP zc1751-xm018-dc4 5 * (C) Copyright 2015 - 2021, Xilinx, Inc. 10 /dts-v1/; 12 #include "zynqmp.dtsi" 13 #include "zynqmp-clk-ccf.dtsi" 16 model = "ZynqMP zc1751-xm018-dc4"; 17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; 26 rtc0 = &rtc; 34 stdout-path = "serial0:115200n8"; [all …]
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D | zynqmp-zc1751-xm016-dc2.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2 5 * (C) Copyright 2015 - 2021, Xilinx, Inc. 10 /dts-v1/; 12 #include "zynqmp.dtsi" 13 #include "zynqmp-clk-ccf.dtsi" 14 #include <dt-bindings/gpio/gpio.h> 15 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 18 model = "ZynqMP zc1751-xm016-dc2 RevA"; 19 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; [all …]
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D | zynqmp-zc1751-xm015-dc1.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1 5 * (C) Copyright 2015 - 2021, Xilinx, Inc. 10 /dts-v1/; 12 #include "zynqmp.dtsi" 13 #include "zynqmp-clk-ccf.dtsi" 14 #include <dt-bindings/phy/phy.h> 15 #include <dt-bindings/gpio/gpio.h> 16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 19 model = "ZynqMP zc1751-xm015-dc1 RevA"; [all …]
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D | zynqmp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP 5 * (C) Copyright 2014 - 2021, Xilinx, Inc. 15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> 16 #include <dt-bindings/power/xlnx-zynqmp-power.h> 17 #include <dt-bindings/reset/xlnx-zynqmp-resets.h> 20 compatible = "xlnx,zynqmp"; 21 #address-cells = <2>; 22 #size-cells = <2>; 25 #address-cells = <1>; [all …]
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D | zynqmp-zcu104-revC.dts | 1 // SPDX-License-Identifier: GPL-2.0 3 * dts file for Xilinx ZynqMP ZCU104 5 * (C) Copyright 2017 - 2021, Xilinx, Inc. 10 /dts-v1/; 12 #include "zynqmp.dtsi" 13 #include "zynqmp-clk-ccf.dtsi" 14 #include <dt-bindings/gpio/gpio.h> 15 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 16 #include <dt-bindings/phy/phy.h> 19 model = "ZynqMP ZCU104 RevC"; [all …]
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D | zynqmp-zcu104-revA.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP ZCU104 5 * (C) Copyright 2017 - 2021, Xilinx, Inc. 10 /dts-v1/; 12 #include "zynqmp.dtsi" 13 #include "zynqmp-clk-ccf.dtsi" 14 #include <dt-bindings/gpio/gpio.h> 15 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 16 #include <dt-bindings/phy/phy.h> 19 model = "ZynqMP ZCU104 RevA"; [all …]
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D | zynqmp-zcu100-revC.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP ZCU100 revC 5 * (C) Copyright 2016 - 2021, Xilinx, Inc. 11 /dts-v1/; 13 #include "zynqmp.dtsi" 14 #include "zynqmp-clk-ccf.dtsi" 15 #include <dt-bindings/input/input.h> 16 #include <dt-bindings/interrupt-controller/irq.h> 17 #include <dt-bindings/gpio/gpio.h> 18 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> [all …]
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D | zynqmp-sm-k26-revA.dts | 1 // SPDX-License-Identifier: GPL-2.0 3 * dts file for Xilinx ZynqMP SM-K26 rev1/B/A 5 * (C) Copyright 2020 - 2021, Xilinx, Inc. 10 /dts-v1/; 12 #include "zynqmp.dtsi" 13 #include "zynqmp-clk-ccf.dtsi" 14 #include <dt-bindings/input/input.h> 15 #include <dt-bindings/gpio/gpio.h> 16 #include <dt-bindings/phy/phy.h> 19 model = "ZynqMP SM-K26 Rev1/B/A"; [all …]
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D | zynqmp-zcu111-revA.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP ZCU111 5 * (C) Copyright 2017 - 2021, Xilinx, Inc. 10 /dts-v1/; 12 #include "zynqmp.dtsi" 13 #include "zynqmp-clk-ccf.dtsi" 14 #include <dt-bindings/input/input.h> 15 #include <dt-bindings/gpio/gpio.h> 16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 17 #include <dt-bindings/phy/phy.h> [all …]
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D | zynqmp-zcu102-revA.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP ZCU102 RevA 5 * (C) Copyright 2015 - 2021, Xilinx, Inc. 10 /dts-v1/; 12 #include "zynqmp.dtsi" 13 #include "zynqmp-clk-ccf.dtsi" 14 #include <dt-bindings/input/input.h> 15 #include <dt-bindings/gpio/gpio.h> 16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 17 #include <dt-bindings/phy/phy.h> [all …]
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D | zynqmp-zcu106-revA.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP ZCU106 5 * (C) Copyright 2016 - 2021, Xilinx, Inc. 10 /dts-v1/; 12 #include "zynqmp.dtsi" 13 #include "zynqmp-clk-ccf.dtsi" 14 #include <dt-bindings/input/input.h> 15 #include <dt-bindings/gpio/gpio.h> 16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 17 #include <dt-bindings/phy/phy.h> [all …]
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/Linux-v6.1/drivers/rtc/ |
D | rtc-zynqmp.c | 1 // SPDX-License-Identifier: GPL-2.0 16 #include <linux/rtc.h> 18 /* RTC Registers */ 47 #define RTC_MIN_OFFSET -32768000 51 struct rtc_device *rtc; member 71 writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR); in xlnx_rtc_set_time() 74 * Clear the rtc interrupt status register after setting the in xlnx_rtc_set_time() 77 * that one second has not elapsed yet since RTC was set and in xlnx_rtc_set_time() 81 writel(RTC_INT_SEC, xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_set_time() 92 status = readl(xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_read_time() [all …]
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D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0 3 # Makefile for RTC class/drivers. 6 ccflags-$(CONFIG_RTC_DEBUG) := -DDEBUG 8 obj-$(CONFIG_RTC_LIB) += lib.o 9 obj-$(CONFIG_RTC_CLASS) += rtc-core.o 10 obj-$(CONFIG_RTC_MC146818_LIB) += rtc-mc146818-lib.o 11 rtc-core-y := class.o interface.o 13 rtc-core-$(CONFIG_RTC_NVMEM) += nvmem.o 14 rtc-core-$(CONFIG_RTC_INTF_DEV) += dev.o 15 rtc-core-$(CONFIG_RTC_INTF_PROC) += proc.o [all …]
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/Linux-v6.1/drivers/spi/ |
D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0 6 ccflags-$(CONFIG_SPI_DEBUG) := -DDEBUG 8 # small core, mostly translating board-specific 10 obj-$(CONFIG_SPI_MASTER) += spi.o 11 obj-$(CONFIG_SPI_MEM) += spi-mem.o 12 obj-$(CONFIG_SPI_MUX) += spi-mux.o 13 obj-$(CONFIG_SPI_SPIDEV) += spidev.o 14 obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-loopback-test.o 17 obj-$(CONFIG_SPI_ALTERA) += spi-altera-platform.o 18 obj-$(CONFIG_SPI_ALTERA_CORE) += spi-altera-core.o [all …]
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D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 13 dynamic device discovery; some are even write-only or read-only. 17 chips, analog to digital (and d-to-a) converters, and more. 44 If your system has an master-capable SPI controller (which 56 by providing a high-level interface to send memory-like commands. 138 supports spi-mem interface. 208 this code to manage the per-word or per-transfer accesses to the 229 used by Xilinx Zynq and ZynqMP. 238 Flash over 1/2/4-bit wide bus. Enable this option if you have a 258 This enables dedicated general purpose SPI/Microwire1-compatible [all …]
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/Linux-v6.1/ |
D | MAINTAINERS | 9 ------------------------- 30 ``diff -u`` to make the patch easy to merge. Be prepared to get your 40 See Documentation/process/coding-style.rst for guidance here. 46 See Documentation/process/submitting-patches.rst for details. 57 include a Signed-off-by: line. The current version of this 59 Documentation/process/submitting-patches.rst. 70 that the bug would present a short-term risk to other users if it 76 Documentation/admin-guide/security-bugs.rst for details. 81 --------------------------------------------------- 97 W: *Web-page* with status/info [all …]
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