Lines Matching +full:zynqmp +full:- +full:rtc
1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm015-dc1 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
27 rtc0 = &rtc;
35 stdout-path = "serial0:115200n8";
43 clock_si5338_0: clk27 { /* u55 SI5338-GM */
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 clock-frequency = <27000000>;
50 compatible = "fixed-clock";
51 #clock-cells = <0>;
52 clock-frequency = <26000000>;
56 compatible = "fixed-clock";
57 #clock-cells = <0>;
58 clock-frequency = <150000000>;
96 phy-handle = <&phy0>;
97 phy-mode = "rgmii-id";
98 pinctrl-names = "default";
99 pinctrl-0 = <&pinctrl_gem3_default>;
100 phy0: ethernet-phy@0 {
107 pinctrl-names = "default";
108 pinctrl-0 = <&pinctrl_gpio_default>;
114 clock-frequency = <400000>;
115 pinctrl-names = "default", "gpio";
116 pinctrl-0 = <&pinctrl_i2c1_default>;
117 pinctrl-1 = <&pinctrl_i2c1_gpio>;
118 scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;
119 sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
129 pinctrl_i2c1_default: i2c1-default {
137 bias-pull-up;
138 slew-rate = <SLEW_RATE_SLOW>;
139 power-source = <IO_STANDARD_LVCMOS18>;
143 pinctrl_i2c1_gpio: i2c1-gpio {
151 slew-rate = <SLEW_RATE_SLOW>;
152 power-source = <IO_STANDARD_LVCMOS18>;
156 pinctrl_uart0_default: uart0-default {
164 slew-rate = <SLEW_RATE_SLOW>;
165 power-source = <IO_STANDARD_LVCMOS18>;
168 conf-rx {
170 bias-high-impedance;
173 conf-tx {
175 bias-disable;
179 pinctrl_usb0_default: usb0-default {
187 slew-rate = <SLEW_RATE_SLOW>;
188 power-source = <IO_STANDARD_LVCMOS18>;
191 conf-rx {
193 bias-high-impedance;
196 conf-tx {
199 bias-disable;
203 pinctrl_gem3_default: gem3-default {
211 slew-rate = <SLEW_RATE_SLOW>;
212 power-source = <IO_STANDARD_LVCMOS18>;
215 conf-rx {
218 bias-high-impedance;
219 low-power-disable;
222 conf-tx {
225 bias-disable;
226 low-power-enable;
229 mux-mdio {
234 conf-mdio {
236 slew-rate = <SLEW_RATE_SLOW>;
237 power-source = <IO_STANDARD_LVCMOS18>;
238 bias-disable;
242 pinctrl_sdhci0_default: sdhci0-default {
250 slew-rate = <SLEW_RATE_SLOW>;
251 power-source = <IO_STANDARD_LVCMOS18>;
252 bias-disable;
255 mux-cd {
260 conf-cd {
262 bias-high-impedance;
263 bias-pull-up;
264 slew-rate = <SLEW_RATE_SLOW>;
265 power-source = <IO_STANDARD_LVCMOS18>;
268 mux-wp {
273 conf-wp {
275 bias-high-impedance;
276 bias-pull-up;
277 slew-rate = <SLEW_RATE_SLOW>;
278 power-source = <IO_STANDARD_LVCMOS18>;
282 pinctrl_sdhci1_default: sdhci1-default {
290 slew-rate = <SLEW_RATE_SLOW>;
291 power-source = <IO_STANDARD_LVCMOS18>;
292 bias-disable;
295 mux-cd {
300 conf-cd {
302 bias-high-impedance;
303 bias-pull-up;
304 slew-rate = <SLEW_RATE_SLOW>;
305 power-source = <IO_STANDARD_LVCMOS18>;
308 mux-wp {
313 conf-wp {
315 bias-high-impedance;
316 bias-pull-up;
317 slew-rate = <SLEW_RATE_SLOW>;
318 power-source = <IO_STANDARD_LVCMOS18>;
322 pinctrl_gpio_default: gpio-default {
330 bias-disable;
331 slew-rate = <SLEW_RATE_SLOW>;
332 power-source = <IO_STANDARD_LVCMOS18>;
341 clock-names = "ref1", "ref2", "ref3";
347 compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */
348 #address-cells = <1>;
349 #size-cells = <1>;
351 spi-tx-bus-width = <1>;
352 spi-rx-bus-width = <4>;
353 spi-max-frequency = <108000000>; /* Based on DC1 spec */
357 &rtc {
364 ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
365 ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
366 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
367 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
368 ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
369 ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
370 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
371 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
372 phy-names = "sata-phy";
379 pinctrl-names = "default";
380 pinctrl-0 = <&pinctrl_sdhci0_default>;
381 bus-width = <8>;
382 xlnx,mio-bank = <0>;
391 no-1-8-v;
392 pinctrl-names = "default";
393 pinctrl-0 = <&pinctrl_sdhci1_default>;
394 xlnx,mio-bank = <1>;
399 pinctrl-names = "default";
400 pinctrl-0 = <&pinctrl_uart0_default>;
406 pinctrl-names = "default";
407 pinctrl-0 = <&pinctrl_usb0_default>;
408 phy-names = "usb3-phy";
416 maximum-speed = "super-speed";
425 phy-names = "dp-phy0", "dp-phy1";