Lines Matching +full:zynqmp +full:- +full:rtc
1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU104
5 * (C) Copyright 2017 - 2021, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
16 #include <dt-bindings/phy/phy.h>
19 model = "ZynqMP ZCU104 RevA";
20 compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
27 rtc0 = &rtc;
37 stdout-path = "serial0:115200n8";
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
48 clock-frequency = <125000000>;
52 compatible = "fixed-clock";
53 #clock-cells = <0>;
54 clock-frequency = <26000000>;
58 compatible = "fixed-clock";
59 #clock-cells = <0>;
60 clock-frequency = <27000000>;
66 pinctrl-names = "default";
67 pinctrl-0 = <&pinctrl_can1_default>;
108 phy-handle = <&phy0>;
109 phy-mode = "rgmii-id";
110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_gem3_default>;
112 phy0: ethernet-phy@c {
114 ti,rx-internal-delay = <0x8>;
115 ti,tx-internal-delay = <0xa>;
116 ti,fifo-depth = <0x1>;
117 ti,dp83867-rxctrl-strap-quirk;
127 clock-frequency = <400000>;
128 pinctrl-names = "default", "gpio";
129 pinctrl-0 = <&pinctrl_i2c1_default>;
130 pinctrl-1 = <&pinctrl_i2c1_gpio>;
131 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
132 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
134 /* Another connection to this bus via PL i2c via PCA9306 - u45 */
135 i2c-mux@74 { /* u34 */
137 #address-cells = <1>;
138 #size-cells = <0>;
141 #address-cells = <1>;
142 #size-cells = <0>;
147 * 0 - 256B address 0x54
148 * 256B - 512B address 0x55
149 * 512B - 768B address 0x56
150 * 768B - 1024B address 0x57
155 #address-cells = <1>;
156 #size-cells = <1>;
161 #address-cells = <1>;
162 #size-cells = <0>;
164 /* 8T49N287 - u182 */
168 #address-cells = <1>;
169 #size-cells = <0>;
171 irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
175 irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
182 #address-cells = <1>;
183 #size-cells = <0>;
188 gpio-controller;
189 #gpio-cells = <2>;
193 * 0 - IRPS5401_ALERT_B
194 * 1 - HDMI_8T49N241_INT_ALM
195 * 2 - MAX6643_OT_B
196 * 3 - MAX6643_FANFAIL_B
197 * 5 - IIC_MUX_RESET_B
198 * 6 - GEM3_EXP_RESET_B
199 * 7 - FMC_LPC_PRSNT_M2C_B
200 * 4, 10 - 17 - not connected
206 #address-cells = <1>;
207 #size-cells = <0>;
212 #address-cells = <1>;
213 #size-cells = <0>;
224 pinctrl_can1_default: can1-default {
232 slew-rate = <SLEW_RATE_SLOW>;
233 power-source = <IO_STANDARD_LVCMOS18>;
234 drive-strength = <12>;
237 conf-rx {
239 bias-high-impedance;
242 conf-tx {
244 bias-disable;
248 pinctrl_i2c1_default: i2c1-default {
256 bias-pull-up;
257 slew-rate = <SLEW_RATE_SLOW>;
258 power-source = <IO_STANDARD_LVCMOS18>;
259 drive-strength = <12>;
263 pinctrl_i2c1_gpio: i2c1-gpio {
271 slew-rate = <SLEW_RATE_SLOW>;
272 power-source = <IO_STANDARD_LVCMOS18>;
273 drive-strength = <12>;
277 pinctrl_gem3_default: gem3-default {
285 slew-rate = <SLEW_RATE_SLOW>;
286 power-source = <IO_STANDARD_LVCMOS18>;
287 drive-strength = <12>;
290 conf-rx {
293 bias-high-impedance;
294 low-power-disable;
297 conf-tx {
300 bias-disable;
301 low-power-enable;
304 mux-mdio {
309 conf-mdio {
311 slew-rate = <SLEW_RATE_SLOW>;
312 power-source = <IO_STANDARD_LVCMOS18>;
313 bias-disable;
317 pinctrl_sdhci1_default: sdhci1-default {
325 slew-rate = <SLEW_RATE_SLOW>;
326 power-source = <IO_STANDARD_LVCMOS18>;
327 bias-disable;
328 drive-strength = <12>;
331 mux-cd {
336 conf-cd {
338 bias-high-impedance;
339 bias-pull-up;
340 slew-rate = <SLEW_RATE_SLOW>;
341 power-source = <IO_STANDARD_LVCMOS18>;
345 pinctrl_uart0_default: uart0-default {
353 slew-rate = <SLEW_RATE_SLOW>;
354 power-source = <IO_STANDARD_LVCMOS18>;
355 drive-strength = <12>;
358 conf-rx {
360 bias-high-impedance;
363 conf-tx {
365 bias-disable;
369 pinctrl_uart1_default: uart1-default {
377 slew-rate = <SLEW_RATE_SLOW>;
378 power-source = <IO_STANDARD_LVCMOS18>;
379 drive-strength = <12>;
382 conf-rx {
384 bias-high-impedance;
387 conf-tx {
389 bias-disable;
393 pinctrl_usb0_default: usb0-default {
401 slew-rate = <SLEW_RATE_SLOW>;
402 power-source = <IO_STANDARD_LVCMOS18>;
403 drive-strength = <12>;
406 conf-rx {
408 bias-high-impedance;
411 conf-tx {
414 bias-disable;
423 clock-names = "ref1", "ref2", "ref3";
429 compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
430 #address-cells = <1>;
431 #size-cells = <1>;
433 spi-tx-bus-width = <1>;
434 spi-rx-bus-width = <4>;
435 spi-max-frequency = <108000000>; /* Based on DC1 spec */
439 &rtc {
446 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
447 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
448 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
449 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
450 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
451 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
452 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
453 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
454 phy-names = "sata-phy";
461 no-1-8-v;
462 pinctrl-names = "default";
463 pinctrl-0 = <&pinctrl_sdhci1_default>;
464 xlnx,mio-bank = <1>;
465 disable-wp;
470 pinctrl-names = "default";
471 pinctrl-0 = <&pinctrl_uart0_default>;
476 pinctrl-names = "default";
477 pinctrl-0 = <&pinctrl_uart1_default>;
483 pinctrl-names = "default";
484 pinctrl-0 = <&pinctrl_usb0_default>;
485 phy-names = "usb3-phy";
493 maximum-speed = "super-speed";
506 phy-names = "dp-phy0", "dp-phy1";