Lines Matching +full:zynqmp +full:- +full:rtc
1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/power/xlnx-zynqmp-power.h>
17 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
20 compatible = "xlnx,zynqmp";
21 #address-cells = <2>;
22 #size-cells = <2>;
25 #address-cells = <1>;
26 #size-cells = <0>;
29 compatible = "arm,cortex-a53";
31 enable-method = "psci";
32 operating-points-v2 = <&cpu_opp_table>;
34 cpu-idle-states = <&CPU_SLEEP_0>;
38 compatible = "arm,cortex-a53";
40 enable-method = "psci";
42 operating-points-v2 = <&cpu_opp_table>;
43 cpu-idle-states = <&CPU_SLEEP_0>;
47 compatible = "arm,cortex-a53";
49 enable-method = "psci";
51 operating-points-v2 = <&cpu_opp_table>;
52 cpu-idle-states = <&CPU_SLEEP_0>;
56 compatible = "arm,cortex-a53";
58 enable-method = "psci";
60 operating-points-v2 = <&cpu_opp_table>;
61 cpu-idle-states = <&CPU_SLEEP_0>;
64 idle-states {
65 entry-method = "psci";
67 CPU_SLEEP_0: cpu-sleep-0 {
68 compatible = "arm,idle-state";
69 arm,psci-suspend-param = <0x40000000>;
70 local-timer-stop;
71 entry-latency-us = <300>;
72 exit-latency-us = <600>;
73 min-residency-us = <10000>;
78 cpu_opp_table: cpu-opp-table {
79 compatible = "operating-points-v2";
80 opp-shared;
82 opp-hz = /bits/ 64 <1199999988>;
83 opp-microvolt = <1000000>;
84 clock-latency-ns = <500000>;
87 opp-hz = /bits/ 64 <599999994>;
88 opp-microvolt = <1000000>;
89 clock-latency-ns = <500000>;
92 opp-hz = /bits/ 64 <399999996>;
93 opp-microvolt = <1000000>;
94 clock-latency-ns = <500000>;
97 opp-hz = /bits/ 64 <299999997>;
98 opp-microvolt = <1000000>;
99 clock-latency-ns = <500000>;
104 compatible = "xlnx,zynqmp-ipi-mailbox";
105 interrupt-parent = <&gic>;
107 xlnx,ipi-id = <0>;
108 #address-cells = <2>;
109 #size-cells = <2>;
117 reg-names = "local_request_region",
121 #mbox-cells = <1>;
122 xlnx,ipi-id = <4>;
132 compatible = "arm,armv8-pmuv3";
133 interrupt-parent = <&gic>;
141 compatible = "arm,psci-0.2";
146 zynqmp_firmware: zynqmp-firmware {
147 compatible = "xlnx,zynqmp-firmware";
148 #power-domain-cells = <1>;
151 zynqmp_power: zynqmp-power {
152 compatible = "xlnx,zynqmp-power";
153 interrupt-parent = <&gic>;
156 mbox-names = "tx", "rx";
160 compatible = "xlnx,zynqmp-nvmem-fw";
161 #address-cells = <1>;
162 #size-cells = <1>;
170 compatible = "xlnx,zynqmp-pcap-fpga";
173 xlnx_aes: zynqmp-aes {
174 compatible = "xlnx,zynqmp-aes";
177 zynqmp_reset: reset-controller {
178 compatible = "xlnx,zynqmp-reset";
179 #reset-cells = <1>;
183 compatible = "xlnx,zynqmp-pinctrl";
190 compatible = "arm,armv8-timer";
191 interrupt-parent = <&gic>;
198 fpga_full: fpga-full {
199 compatible = "fpga-region";
200 fpga-mgr = <&zynqmp_pcap>;
201 #address-cells = <2>;
202 #size-cells = <2>;
207 compatible = "simple-bus";
208 #address-cells = <2>;
209 #size-cells = <2>;
213 compatible = "xlnx,zynq-can-1.0";
215 clock-names = "can_clk", "pclk";
218 interrupt-parent = <&gic>;
219 tx-fifo-depth = <0x40>;
220 rx-fifo-depth = <0x40>;
221 power-domains = <&zynqmp_firmware PD_CAN_0>;
225 compatible = "xlnx,zynq-can-1.0";
227 clock-names = "can_clk", "pclk";
230 interrupt-parent = <&gic>;
231 tx-fifo-depth = <0x40>;
232 rx-fifo-depth = <0x40>;
233 power-domains = <&zynqmp_firmware PD_CAN_1>;
237 compatible = "arm,cci-400";
241 #address-cells = <1>;
242 #size-cells = <1>;
245 compatible = "arm,cci-400-pmu,r1";
247 interrupt-parent = <&gic>;
257 fpd_dma_chan1: dma-controller@fd500000 {
259 compatible = "xlnx,zynqmp-dma-1.0";
261 interrupt-parent = <&gic>;
263 clock-names = "clk_main", "clk_apb";
264 #dma-cells = <1>;
265 xlnx,bus-width = <128>;
267 power-domains = <&zynqmp_firmware PD_GDMA>;
270 fpd_dma_chan2: dma-controller@fd510000 {
272 compatible = "xlnx,zynqmp-dma-1.0";
274 interrupt-parent = <&gic>;
276 clock-names = "clk_main", "clk_apb";
277 #dma-cells = <1>;
278 xlnx,bus-width = <128>;
280 power-domains = <&zynqmp_firmware PD_GDMA>;
283 fpd_dma_chan3: dma-controller@fd520000 {
285 compatible = "xlnx,zynqmp-dma-1.0";
287 interrupt-parent = <&gic>;
289 clock-names = "clk_main", "clk_apb";
290 #dma-cells = <1>;
291 xlnx,bus-width = <128>;
293 power-domains = <&zynqmp_firmware PD_GDMA>;
296 fpd_dma_chan4: dma-controller@fd530000 {
298 compatible = "xlnx,zynqmp-dma-1.0";
300 interrupt-parent = <&gic>;
302 clock-names = "clk_main", "clk_apb";
303 #dma-cells = <1>;
304 xlnx,bus-width = <128>;
306 power-domains = <&zynqmp_firmware PD_GDMA>;
309 fpd_dma_chan5: dma-controller@fd540000 {
311 compatible = "xlnx,zynqmp-dma-1.0";
313 interrupt-parent = <&gic>;
315 clock-names = "clk_main", "clk_apb";
316 #dma-cells = <1>;
317 xlnx,bus-width = <128>;
319 power-domains = <&zynqmp_firmware PD_GDMA>;
322 fpd_dma_chan6: dma-controller@fd550000 {
324 compatible = "xlnx,zynqmp-dma-1.0";
326 interrupt-parent = <&gic>;
328 clock-names = "clk_main", "clk_apb";
329 #dma-cells = <1>;
330 xlnx,bus-width = <128>;
332 power-domains = <&zynqmp_firmware PD_GDMA>;
335 fpd_dma_chan7: dma-controller@fd560000 {
337 compatible = "xlnx,zynqmp-dma-1.0";
339 interrupt-parent = <&gic>;
341 clock-names = "clk_main", "clk_apb";
342 #dma-cells = <1>;
343 xlnx,bus-width = <128>;
345 power-domains = <&zynqmp_firmware PD_GDMA>;
348 fpd_dma_chan8: dma-controller@fd570000 {
350 compatible = "xlnx,zynqmp-dma-1.0";
352 interrupt-parent = <&gic>;
354 clock-names = "clk_main", "clk_apb";
355 #dma-cells = <1>;
356 xlnx,bus-width = <128>;
358 power-domains = <&zynqmp_firmware PD_GDMA>;
361 gic: interrupt-controller@f9010000 {
362 compatible = "arm,gic-400";
363 #address-cells = <0>;
364 #interrupt-cells = <3>;
369 interrupt-controller;
370 interrupt-parent = <&gic>;
378 lpd_dma_chan1: dma-controller@ffa80000 {
380 compatible = "xlnx,zynqmp-dma-1.0";
382 interrupt-parent = <&gic>;
384 clock-names = "clk_main", "clk_apb";
385 #dma-cells = <1>;
386 xlnx,bus-width = <64>;
388 power-domains = <&zynqmp_firmware PD_ADMA>;
391 lpd_dma_chan2: dma-controller@ffa90000 {
393 compatible = "xlnx,zynqmp-dma-1.0";
395 interrupt-parent = <&gic>;
397 clock-names = "clk_main", "clk_apb";
398 #dma-cells = <1>;
399 xlnx,bus-width = <64>;
401 power-domains = <&zynqmp_firmware PD_ADMA>;
404 lpd_dma_chan3: dma-controller@ffaa0000 {
406 compatible = "xlnx,zynqmp-dma-1.0";
408 interrupt-parent = <&gic>;
410 clock-names = "clk_main", "clk_apb";
411 #dma-cells = <1>;
412 xlnx,bus-width = <64>;
414 power-domains = <&zynqmp_firmware PD_ADMA>;
417 lpd_dma_chan4: dma-controller@ffab0000 {
419 compatible = "xlnx,zynqmp-dma-1.0";
421 interrupt-parent = <&gic>;
423 clock-names = "clk_main", "clk_apb";
424 #dma-cells = <1>;
425 xlnx,bus-width = <64>;
427 power-domains = <&zynqmp_firmware PD_ADMA>;
430 lpd_dma_chan5: dma-controller@ffac0000 {
432 compatible = "xlnx,zynqmp-dma-1.0";
434 interrupt-parent = <&gic>;
436 clock-names = "clk_main", "clk_apb";
437 #dma-cells = <1>;
438 xlnx,bus-width = <64>;
440 power-domains = <&zynqmp_firmware PD_ADMA>;
443 lpd_dma_chan6: dma-controller@ffad0000 {
445 compatible = "xlnx,zynqmp-dma-1.0";
447 interrupt-parent = <&gic>;
449 clock-names = "clk_main", "clk_apb";
450 #dma-cells = <1>;
451 xlnx,bus-width = <64>;
453 power-domains = <&zynqmp_firmware PD_ADMA>;
456 lpd_dma_chan7: dma-controller@ffae0000 {
458 compatible = "xlnx,zynqmp-dma-1.0";
460 interrupt-parent = <&gic>;
462 clock-names = "clk_main", "clk_apb";
463 #dma-cells = <1>;
464 xlnx,bus-width = <64>;
466 power-domains = <&zynqmp_firmware PD_ADMA>;
469 lpd_dma_chan8: dma-controller@ffaf0000 {
471 compatible = "xlnx,zynqmp-dma-1.0";
473 interrupt-parent = <&gic>;
475 clock-names = "clk_main", "clk_apb";
476 #dma-cells = <1>;
477 xlnx,bus-width = <64>;
479 power-domains = <&zynqmp_firmware PD_ADMA>;
482 mc: memory-controller@fd070000 {
483 compatible = "xlnx,zynqmp-ddrc-2.40a";
485 interrupt-parent = <&gic>;
489 nand0: nand-controller@ff100000 {
490 compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10";
493 clock-names = "controller", "bus";
494 interrupt-parent = <&gic>;
496 #address-cells = <1>;
497 #size-cells = <0>;
499 power-domains = <&zynqmp_firmware PD_NAND>;
503 compatible = "cdns,zynqmp-gem", "cdns,gem";
505 interrupt-parent = <&gic>;
508 clock-names = "pclk", "hclk", "tx_clk";
509 #address-cells = <1>;
510 #size-cells = <0>;
512 power-domains = <&zynqmp_firmware PD_ETH_0>;
514 reset-names = "gem0_rst";
518 compatible = "cdns,zynqmp-gem", "cdns,gem";
520 interrupt-parent = <&gic>;
523 clock-names = "pclk", "hclk", "tx_clk";
524 #address-cells = <1>;
525 #size-cells = <0>;
527 power-domains = <&zynqmp_firmware PD_ETH_1>;
529 reset-names = "gem1_rst";
533 compatible = "cdns,zynqmp-gem", "cdns,gem";
535 interrupt-parent = <&gic>;
538 clock-names = "pclk", "hclk", "tx_clk";
539 #address-cells = <1>;
540 #size-cells = <0>;
542 power-domains = <&zynqmp_firmware PD_ETH_2>;
544 reset-names = "gem2_rst";
548 compatible = "cdns,zynqmp-gem", "cdns,gem";
550 interrupt-parent = <&gic>;
553 clock-names = "pclk", "hclk", "tx_clk";
554 #address-cells = <1>;
555 #size-cells = <0>;
557 power-domains = <&zynqmp_firmware PD_ETH_3>;
559 reset-names = "gem3_rst";
563 compatible = "xlnx,zynqmp-gpio-1.0";
565 #address-cells = <0>;
566 #gpio-cells = <0x2>;
567 gpio-controller;
568 interrupt-parent = <&gic>;
570 interrupt-controller;
571 #interrupt-cells = <2>;
573 power-domains = <&zynqmp_firmware PD_GPIO>;
577 compatible = "cdns,i2c-r1p14";
579 interrupt-parent = <&gic>;
582 #address-cells = <1>;
583 #size-cells = <0>;
584 power-domains = <&zynqmp_firmware PD_I2C_0>;
588 compatible = "cdns,i2c-r1p14";
590 interrupt-parent = <&gic>;
593 #address-cells = <1>;
594 #size-cells = <0>;
595 power-domains = <&zynqmp_firmware PD_I2C_1>;
599 compatible = "xlnx,nwl-pcie-2.11";
601 #address-cells = <3>;
602 #size-cells = <2>;
603 #interrupt-cells = <1>;
604 msi-controller;
606 interrupt-parent = <&gic>;
612 interrupt-names = "misc", "dummy", "intx",
614 msi-parent = <&pcie>;
618 reg-names = "breg", "pcireg", "cfg";
619 …ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-pre…
621 bus-range = <0x00 0xff>;
622 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
623 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
628 power-domains = <&zynqmp_firmware PD_PCIE>;
629 pcie_intc: legacy-interrupt-controller {
630 interrupt-controller;
631 #address-cells = <0>;
632 #interrupt-cells = <1>;
637 compatible = "xlnx,zynqmp-qspi-1.0";
639 clock-names = "ref_clk", "pclk";
641 interrupt-parent = <&gic>;
642 num-cs = <1>;
645 #address-cells = <1>;
646 #size-cells = <0>;
648 power-domains = <&zynqmp_firmware PD_QSPI>;
652 compatible = "xlnx,zynqmp-psgtr-v1.1";
656 reg-names = "serdes", "siou";
657 #phy-cells = <4>;
660 rtc: rtc@ffa60000 { label
661 compatible = "xlnx,zynqmp-rtc";
664 interrupt-parent = <&gic>;
666 interrupt-names = "alarm", "sec";
671 compatible = "ceva,ahci-1v84";
674 interrupt-parent = <&gic>;
676 power-domains = <&zynqmp_firmware PD_SATA>;
683 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
685 interrupt-parent = <&gic>;
688 clock-names = "clk_xin", "clk_ahb";
690 #clock-cells = <1>;
691 clock-output-names = "clk_out_sd0", "clk_in_sd0";
692 power-domains = <&zynqmp_firmware PD_SD_0>;
696 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
698 interrupt-parent = <&gic>;
701 clock-names = "clk_xin", "clk_ahb";
703 #clock-cells = <1>;
704 clock-output-names = "clk_out_sd1", "clk_in_sd1";
705 power-domains = <&zynqmp_firmware PD_SD_1>;
709 compatible = "arm,mmu-500";
711 #iommu-cells = <1>;
713 #global-interrupts = <1>;
714 interrupt-parent = <&gic>;
723 compatible = "cdns,spi-r1p6";
725 interrupt-parent = <&gic>;
728 clock-names = "ref_clk", "pclk";
729 #address-cells = <1>;
730 #size-cells = <0>;
731 power-domains = <&zynqmp_firmware PD_SPI_0>;
735 compatible = "cdns,spi-r1p6";
737 interrupt-parent = <&gic>;
740 clock-names = "ref_clk", "pclk";
741 #address-cells = <1>;
742 #size-cells = <0>;
743 power-domains = <&zynqmp_firmware PD_SPI_1>;
749 interrupt-parent = <&gic>;
752 timer-width = <32>;
753 power-domains = <&zynqmp_firmware PD_TTC_0>;
759 interrupt-parent = <&gic>;
762 timer-width = <32>;
763 power-domains = <&zynqmp_firmware PD_TTC_1>;
769 interrupt-parent = <&gic>;
772 timer-width = <32>;
773 power-domains = <&zynqmp_firmware PD_TTC_2>;
779 interrupt-parent = <&gic>;
782 timer-width = <32>;
783 power-domains = <&zynqmp_firmware PD_TTC_3>;
787 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
789 interrupt-parent = <&gic>;
792 clock-names = "uart_clk", "pclk";
793 power-domains = <&zynqmp_firmware PD_UART_0>;
797 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
799 interrupt-parent = <&gic>;
802 clock-names = "uart_clk", "pclk";
803 power-domains = <&zynqmp_firmware PD_UART_1>;
807 #address-cells = <2>;
808 #size-cells = <2>;
810 compatible = "xlnx,zynqmp-dwc3";
812 power-domains = <&zynqmp_firmware PD_USB_0>;
816 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
822 interrupt-parent = <&gic>;
823 interrupt-names = "dwc_usb3", "otg";
825 clock-names = "bus_early", "ref";
827 snps,quirk-frame-length-adjustment = <0x20>;
828 /* dma-coherent; */
833 #address-cells = <2>;
834 #size-cells = <2>;
836 compatible = "xlnx,zynqmp-dwc3";
838 power-domains = <&zynqmp_firmware PD_USB_1>;
842 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
848 interrupt-parent = <&gic>;
849 interrupt-names = "dwc_usb3", "otg";
851 clock-names = "bus_early", "ref";
853 snps,quirk-frame-length-adjustment = <0x20>;
854 /* dma-coherent; */
859 compatible = "cdns,wdt-r1p2";
861 interrupt-parent = <&gic>;
864 timeout-sec = <60>;
865 reset-on-timeout;
869 compatible = "cdns,wdt-r1p2";
871 interrupt-parent = <&gic>;
874 timeout-sec = <10>;
878 compatible = "xlnx,zynqmp-ams";
880 interrupt-parent = <&gic>;
883 #address-cells = <1>;
884 #size-cells = <1>;
885 #io-channel-cells = <1>;
889 compatible = "xlnx,zynqmp-ams-ps";
895 compatible = "xlnx,zynqmp-ams-pl";
898 #address-cells = <1>;
899 #size-cells = <0>;
903 zynqmp_dpdma: dma-controller@fd4c0000 {
904 compatible = "xlnx,zynqmp-dpdma";
908 interrupt-parent = <&gic>;
909 clock-names = "axi_clk";
910 power-domains = <&zynqmp_firmware PD_DP>;
911 #dma-cells = <1>;
915 compatible = "xlnx,zynqmp-dpsub-1.7";
921 reg-names = "dp", "blend", "av_buf", "aud";
923 interrupt-parent = <&gic>;
924 clock-names = "dp_apb_clk", "dp_aud_clk",
926 power-domains = <&zynqmp_firmware PD_DP>;
928 dma-names = "vid0", "vid1", "vid2", "gfx0";