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/Linux-v5.10/drivers/staging/axis-fifo/
Daxis-fifo.txt1 Xilinx AXI-Stream FIFO v4.1 IP core
3 This IP core has read and write AXI-Stream FIFOs, the contents of which can
4 be accessed from the AXI4 memory-mapped interface. This is useful for
11 Currently supports only store-forward mode with a 32-bit
12 AXI4-Lite interface. DOES NOT support:
13 - cut-through mode
14 - AXI4 (non-lite)
17 - compatible: Should be "xlnx,axi-fifo-mm-s-4.1"
18 - interrupt-names: Should be "interrupt"
19 - interrupt-parent: Should be <&intc>
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/usb/
Ddwc3.txt3 DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
7 - compatible: must be "snps,dwc3"
8 - reg : Address and length of the register set for the device
9 - interrupts: Interrupts used by the dwc3 controller.
10 - clock-names: list of clock names. Ideally should be "ref",
12 - clocks: list of phandle and clock specifier pairs corresponding to
13 entries in the clock-names property.
16 clocks are optional if the parent node (i.e. glue-layer) is compatible to
18 "cavium,octeon-7130-usb-uctl"
20 "samsung,exynos5250-dwusb3"
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/Linux-v5.10/drivers/net/wireless/intel/iwlwifi/fw/api/
Dpower.h8 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
10 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH
11 * Copyright (C) 2018 - 2020 Intel Corporation
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
32 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
33 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH
34 * Copyright (C) 2018 - 2020 Intel Corporation
71 * enum iwl_ltr_config_flags - masks for LTR config command flags
[all …]
/Linux-v5.10/drivers/net/wireless/broadcom/b43/
Dphy_n.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 /* N-PHY registers. */
15 #define B43_NPHY_TXERR B43_PHY_N(0x007) /* TX error */
18 #define B43_NPHY_4WI_ADDR B43_PHY_N(0x00B) /* Four-wire bus address */
19 #define B43_NPHY_4WI_DATAHI B43_PHY_N(0x00C) /* Four-wire bus data high */
20 #define B43_NPHY_4WI_DATALO B43_PHY_N(0x00D) /* Four-wire bus data low */
21 #define B43_NPHY_BIST_STAT0 B43_PHY_N(0x00E) /* Built-in self test status 0 */
22 #define B43_NPHY_BIST_STAT1 B43_PHY_N(0x00F) /* Built-in self test status 1 */
58 #define B43_NPHY_C1_INITGAIN_TRTX 0x2000 /* TR TX index */
70 #define B43_NPHY_C1_CLIPWBTHRES B43_PHY_N(0x027) /* Core 1 clip wideband threshold */
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/Linux-v5.10/sound/soc/ti/
Domap-mcbsp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
24 #include "omap-mcbsp-priv.h"
25 #include "omap-mcbsp.h"
26 #include "sdma-pcm.h"
41 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id); in omap_mcbsp_dump_reg()
42 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n", MCBSP_READ(mcbsp, DRR2)); in omap_mcbsp_dump_reg()
43 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n", MCBSP_READ(mcbsp, DRR1)); in omap_mcbsp_dump_reg()
44 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n", MCBSP_READ(mcbsp, DXR2)); in omap_mcbsp_dump_reg()
45 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n", MCBSP_READ(mcbsp, DXR1)); in omap_mcbsp_dump_reg()
[all …]
Domap-mcpdm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap-mcpdm.c -- OMAP ALSA SoC DAI driver using McPDM port
5 * Copyright (C) 2009 - 2011 Texas Instruments
30 #include "omap-mcpdm.h"
31 #include "sdma-pcm.h"
35 u32 threshold; /* FIFO threshold */ member
69 writel_relaxed(val, mcpdm->io_base + reg); in omap_mcpdm_write()
74 return readl_relaxed(mcpdm->io_base + reg); in omap_mcpdm_read()
80 dev_dbg(mcpdm->dev, "***********************\n"); in omap_mcpdm_reg_dump()
81 dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n", in omap_mcpdm_reg_dump()
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/Linux-v5.10/include/linux/soc/ti/
Dknav_dma.h25 #define MASK(x) (BIT(x) - 1)
54 /* Tx channel scheduling priority */
68 /* Rx flow size threshold configuration */
83 * struct knav_dma_tx_cfg: Tx channel configuration
86 * @knav_dma_tx_priority: Tx channel scheduling priority
103 * @thresh: Rx flow size threshold
105 * @sz_thresh0: RX packet size threshold 0
106 * @sz_thresh1: RX packet size threshold 1
107 * @sz_thresh2: RX packet size threshold 2
127 * @tx: Tx channel configuration
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/Linux-v5.10/drivers/net/wireless/ralink/rt2x00/
Drt2500pci.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
36 * Default offset is required for RSSI <-> dBm conversion.
53 * Number of TX queues.
122 * TXDONE_TXRING: Tx ring transmit done interrupt.
128 * UART1_TX_TRESHOLD: UART1 TX reaches threshold.
129 * UART1_RX_TRESHOLD: UART1 RX reaches threshold.
130 * UART1_IDLE_TRESHOLD: UART1 IDLE over threshold.
131 * UART1_TX_BUFF_ERROR: UART1 TX buffer error.
133 * UART2_TX_TRESHOLD: UART2 TX reaches threshold.
[all …]
/Linux-v5.10/drivers/net/wireless/intel/iwlwifi/
Diwl-config.h8 * Copyright (C) 2016 - 2017 Intel Deutschland GmbH
9 * Copyright(c) 2007 - 2014, 2018 - 2020 Intel Corporation
25 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
29 * Copyright (C) 2016 - 2017 Intel Deutschland GmbH
30 * Copyright(c) 2005 - 2014, 2018 - 2020 Intel Corporation
67 #include "iwl-csr.h"
109 * enum iwl_nvm_type - nvm formats
121 * This is the threshold value of plcp error rate per 100mSecs. It is
131 /* TX queue watchdog timeouts in mSecs */
162 * struct iwl_base_params - params not likely to change within a device family
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/Linux-v5.10/drivers/net/ethernet/intel/igb/
De1000_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
7 #define E1000_CTRL 0x00000 /* Device Control - RW */
8 #define E1000_STATUS 0x00008 /* Device Status - RO */
9 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
10 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
11 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
12 #define E1000_MDIC 0x00020 /* MDI Control - RW */
13 #define E1000_MDICNFG 0x00E04 /* MDI Config - RW */
14 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
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/Linux-v5.10/drivers/net/wireless/ti/wlcore/
Dconf.h1 /* SPDX-License-Identifier: GPL-2.0-only */
117 * Range: 0 - 0xFFFFFFFF
122 * Packet detection threshold in the PHY.
130 * after a PS-poll has been transmitted.
132 * Range: 0 - 200000
139 * Range: 0 - 200000
147 * Range: 0 - 4096
152 * The RX Clear Channel Assessment threshold in the PHY
153 * (the energy threshold).
161 * Occupied Rx mem-blocks number which requires interrupting the host
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/Linux-v5.10/include/linux/platform_data/
Dxilinx-ll-temac.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 bool txcsum; /* Enable/disable TX checksum */
20 /* Pre-initialized mutex to use for synchronizing indirect
27 u8 tx_irq_timeout; /* TX Interrupt Delay Time-out */
28 u8 tx_irq_count; /* TX Interrupt Coalescing Threshold Count */
29 u8 rx_irq_timeout; /* RX Interrupt Delay Time-out */
30 u8 rx_irq_count; /* RX Interrupt Coalescing Threshold Count */
/Linux-v5.10/drivers/net/ethernet/cortina/
Dgemini.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
6 * Copyright (C) 2010 Michał Mirosław <mirq-linux@rere.qmqm.pl>
49 * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
58 #define __RWPTR_PREV(x, mask) (((unsigned int)(x) - 1) & (mask))
59 #define __RWPTR_DISTANCE(r, w, mask) (((unsigned int)(w) - (r)) & (mask))
60 #define __RWPTR_MASK(order) ((1 << (order)) - 1)
145 /* GMAC Hash/Rx/Tx AHB Weighting register */
274 #define TOE_QH_FULL_INT_BIT(x) BIT(x - 32)
321 /* 7:0 Software Free Queue Empty Threshold */
[all …]
/Linux-v5.10/drivers/net/ethernet/altera/
Daltera_tse.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Altera Triple-Speed Ethernet MAC driver
3 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
32 #define ALTERA_TSE_MAC_FIFO_WIDTH 4 /* TX/RX FIFO width in
41 /* Tx FIFO default settings */
130 u32 auto_negotiation_advertisement; /* Auto-negotiation
182 /* 32-bit primary MAC address word 0 bits 0 to 31 of the primary
186 /* 32-bit primary MAC address word 1 bits 32 to 47 of the primary
190 /* 14-bit maximum frame length. The MAC receive logic */
196 /* 12-bit receive FIFO section-empty threshold */
[all …]
/Linux-v5.10/drivers/net/ethernet/aquantia/atlantic/hw_atl/
Dhw_atl_llh.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2014-2019 aQuantia Corporation
5 * Copyright (C) 2019-2020 Marvell International Ltd.
65 /* get tx dma good octet counter */
68 /* get tx dma good packet counter */
89 /* get msm tx errors counter register */
92 /* get msm tx unicast frames counter register */
95 /* get msm tx multicast frames counter register */
98 /* get msm tx broadcast frames counter register */
101 /* get msm tx multicast octets counter register 1 */
[all …]
/Linux-v5.10/drivers/net/wireless/ath/ath5k/
Dreg.h2 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
3 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
4 * Copyright (c) 2007-2008 Michael Taylor <mike.taylor@apprion.com>
28 * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf
30 * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf
33 * Atheros's ART program (Atheros Radio Test), on ath9k, on legacy-hal
42 * AR5210-Specific TXDP registers
46 #define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */
47 #define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */
53 #define AR5K_CR_TXE0 0x00000001 /* TX Enable for queue 0 on 5210 */
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/Linux-v5.10/drivers/net/ethernet/oki-semi/pch_gbe/
Dpch_gbe.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 1999 - 2010 Intel Corporation.
26 * pch_gbe_regs_mac_adr - Structure holding values of mac address registers
35 * pch_udc_regs - Structure holding values of MAC registers
118 #define PCH_GBE_TX_RST 0x00008000 /* TX MAC, TX FIFO, TX DMA reset */
124 #define PCH_GBE_TX_TCPIPACC_EN 0x00000002 /* TX TCP/IP ACC Enable */
140 /* Receive Almost Empty Threshold */
145 /* Receive Almost Full Threshold */
150 /* RX FIFO Read Trigger Threshold */
202 /* TX Mode */
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/net/
Dmarvell-armada-370-neta.txt4 - compatible: could be one of the following:
5 "marvell,armada-370-neta"
6 "marvell,armada-xp-neta"
7 "marvell,armada-3700-neta"
8 - reg: address and length of the register set for the device.
9 - interrupts: interrupt for the device
10 - phy: See ethernet.txt file in the same directory.
11 - phy-mode: See ethernet.txt file in the same directory
12 - clocks: List of clocks for this device. At least one clock is
14 clock-names property must be used to identify them.
[all …]
/Linux-v5.10/drivers/net/ethernet/intel/ixgb/
Dixgb_param.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2008 Intel Corporation. */
14 #define OPTION_UNSET -1
33 * Valid Range: 64-4096
42 * Valid Range: 64-4096
51 * Valid Range: 0-3
52 * - 0 - No Flow Control
53 * - 1 - Rx only, respond to PAUSE frames but do not generate them
54 * - 2 - Tx only, generate PAUSE frames but ignore them on receive
55 * - 3 - Full Flow Control Support
[all …]
/Linux-v5.10/drivers/net/ethernet/freescale/
Dfec.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * fec.h -- Fast Ethernet Controller for Motorola ColdFire SoC
8 * (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
9 * (C) Copyright 2000-2001, Lineo (www.lineo.com)
43 #define FEC_TXIC0 0x0f0 /* Tx Interrupt Coalescing for ring 0 */
44 #define FEC_TXIC1 0x0f4 /* Tx Interrupt Coalescing for ring 1 */
45 #define FEC_TXIC2 0x0f8 /* Tx Interrupt Coalescing for ring 2 */
65 #define FEC_R_FIFO_RSFL 0x190 /* Receive FIFO section full threshold */
66 #define FEC_R_FIFO_RSEM 0x194 /* Receive FIFO section empty threshold */
67 #define FEC_R_FIFO_RAEM 0x198 /* Receive FIFO almost empty threshold */
[all …]
/Linux-v5.10/include/soc/fsl/qe/
Dimmap_qe.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
21 /* QE I-RAM */
23 __be32 iadd; /* I-RAM Address Register */
24 __be32 idata; /* I-RAM Data Register */
26 __be32 iready; /* I-RAM Ready Register */
62 __be32 cetscr; /* QE time-stamp timer control register */
63 __be32 cetsr1; /* QE time-stamp register 1 */
64 __be32 cetsr2; /* QE time-stamp register 2 */
166 u8 sitarc1; /* SI1 RAM counter Tx TDMA */
167 u8 sitbrc1; /* SI1 RAM counter Tx TDMB */
[all …]
/Linux-v5.10/drivers/spi/
Dspi-zynq-qspi.c1 // SPDX-License-Identifier: GPL-2.0+
18 #include <linux/spi/spi-mem.h>
28 #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst, WO */
29 #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst, WO */
30 #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst, WO */
31 #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst, WO */
34 #define ZYNQ_QSPI_TX_THRESH_OFFSET 0x28 /* TX FIFO Watermark Reg, RW */
47 #define ZYNQ_QSPI_CONFIG_MANSRT_MASK BIT(16) /* Manual TX Start */
48 #define ZYNQ_QSPI_CONFIG_MANSRTEN_MASK BIT(15) /* Enable Manual TX Mode */
57 * QSPI Configuration Register - Baud rate and slave select
[all …]
/Linux-v5.10/arch/arm64/boot/dts/amlogic/
Dmeson-gxbb-p200.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-gxbb-p20x.dtsi"
11 #include <dt-bindings/input/input.h>
14 compatible = "amlogic,p200", "amlogic,meson-gxbb";
17 avdd18_usb_adc: regulator-avdd18_usb_adc {
18 compatible = "regulator-fixed";
19 regulator-name = "AVDD18_USB_ADC";
20 regulator-min-microvolt = <1800000>;
21 regulator-max-microvolt = <1800000>;
[all …]
/Linux-v5.10/drivers/i2c/busses/
Di2c-nomadik.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2009 ST-Ericsson SA
25 #define DRIVER_NAME "nmk-i2c"
52 #define I2C_CR_DMA_TX_EN (0x1 << 9) /* DMA Tx enable */
61 #define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */
62 #define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */
100 /* maximum threshold value */
111 * struct i2c_vendor_data - per-vendor variations
135 * struct i2c_nmk_client - client specific data
136 * @slave_adr: 7-bit slave address
[all …]
/Linux-v5.10/drivers/net/ethernet/intel/e1000/
De1000_hw.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
425 /* MAC decode size is 128K - This is the size of BAR0 */
446 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
464 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
475 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
489 * E1000_RAR_ENTRIES - 1 multicast addresses.
506 /* Receive Descriptor - Extended */
532 /* Receive Descriptor - Packet Split */
556 __le16 length[3]; /* length of buffers 1-3 */
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