1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (C) 2009 ST-Ericsson SA
25 #define DRIVER_NAME "nmk-i2c"
52 #define I2C_CR_DMA_TX_EN	(0x1 << 9)	/* DMA Tx enable */
61 #define I2C_MCR_A7		(0x7f << 1)	/* 7-bit address */
62 #define I2C_MCR_EA10		(0x7 << 8)	/* 10-bit Extended address */
100 /* maximum threshold value */
111  * struct i2c_vendor_data - per-vendor variations
135  * struct i2c_nmk_client - client specific data
136  * @slave_adr: 7-bit slave address
151  * struct nmk_i2c_dev - private data structure of the controller.
160  * @tft: Tx FIFO Threshold in bytes
161  * @rft: Rx FIFO Threshold in bytes
208  * flush_i2c_fifo() - This function flushes the I2C FIFO
211  * This function flushes the I2C Tx and Rx FIFOs. It returns
224 	 * bits, until then no one must access Tx, Rx FIFO and  in flush_i2c_fifo()
227 	writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR);  in flush_i2c_fifo()
230 		timeout = jiffies + dev->adap.timeout;  in flush_i2c_fifo()
233 			if ((readl(dev->virtbase + I2C_CR) &  in flush_i2c_fifo()
239 	dev_err(&dev->adev->dev,  in flush_i2c_fifo()
243 	return -ETIMEDOUT;  in flush_i2c_fifo()
247  * disable_all_interrupts() - Disable all interrupts of this I2c Bus
253 	writel(mask, dev->virtbase + I2C_IMSCR);  in disable_all_interrupts()
257  * clear_all_interrupts() - Clear all interrupts of I2C Controller
264 	writel(mask, dev->virtbase + I2C_ICR);  in clear_all_interrupts()
268  * init_hw() - initialize the I2C hardware
280 	i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE);  in init_hw()
286 	dev->cli.operation = I2C_NO_OPERATION;  in init_hw()
296  * load_i2c_mcr_reg() - load the MCR register
305 	mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1);  in load_i2c_mcr_reg()
308 		/* 10-bit address transaction */  in load_i2c_mcr_reg()
316 		slave_adr_3msb_bits = (dev->cli.slave_adr >> 7) & 0x7;  in load_i2c_mcr_reg()
320 		/* 7-bit address transaction */  in load_i2c_mcr_reg()
328 	if (dev->cli.operation == I2C_WRITE)  in load_i2c_mcr_reg()
334 	if (dev->stop)  in load_i2c_mcr_reg()
339 	mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15);  in load_i2c_mcr_reg()
345  * setup_i2c_controller() - setup the controller
355 	writel(0x0, dev->virtbase + I2C_CR);  in setup_i2c_controller()
356 	writel(0x0, dev->virtbase + I2C_HSMCR);  in setup_i2c_controller()
357 	writel(0x0, dev->virtbase + I2C_TFTR);  in setup_i2c_controller()
358 	writel(0x0, dev->virtbase + I2C_RFTR);  in setup_i2c_controller()
359 	writel(0x0, dev->virtbase + I2C_DMAR);  in setup_i2c_controller()
361 	i2c_clk = clk_get_rate(dev->clk);  in setup_i2c_controller()
376 	switch (dev->sm) {  in setup_i2c_controller()
391 	dev_dbg(&dev->adev->dev, "calculated SLSU = %04x\n", slsu);  in setup_i2c_controller()
392 	writel(slsu << 16, dev->virtbase + I2C_SCR);  in setup_i2c_controller()
397 	 * operation. TODO - high speed support.  in setup_i2c_controller()
399 	div = (dev->clk_freq > I2C_MAX_STANDARD_MODE_FREQ) ? 3 : 2;  in setup_i2c_controller()
409 	brcr2 = (i2c_clk/(dev->clk_freq * div)) & 0xffff;  in setup_i2c_controller()
412 	writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);  in setup_i2c_controller()
417 	 * TODO - support for fast mode plus (up to 1Mb/s)  in setup_i2c_controller()
420 	if (dev->sm > I2C_FREQ_MODE_FAST) {  in setup_i2c_controller()
421 		dev_err(&dev->adev->dev,  in setup_i2c_controller()
424 		writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);  in setup_i2c_controller()
426 				dev->virtbase + I2C_CR);  in setup_i2c_controller()
428 	writel(dev->sm << 4, dev->virtbase + I2C_CR);  in setup_i2c_controller()
430 	/* set the Tx and Rx FIFO threshold */  in setup_i2c_controller()
431 	writel(dev->tft, dev->virtbase + I2C_TFTR);  in setup_i2c_controller()
432 	writel(dev->rft, dev->virtbase + I2C_RFTR);  in setup_i2c_controller()
436  * read_i2c() - Read from I2C client device
451 	writel(mcr, dev->virtbase + I2C_MCR);  in read_i2c()
454 	writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,  in read_i2c()
455 			dev->virtbase + I2C_CR);  in read_i2c()
458 	i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE);  in read_i2c()
460 	init_completion(&dev->xfer_complete);  in read_i2c()
466 	if (dev->stop || !dev->vendor->has_mtdws)  in read_i2c()
473 	writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,  in read_i2c()
474 			dev->virtbase + I2C_IMSCR);  in read_i2c()
477 		&dev->xfer_complete, dev->adap.timeout);  in read_i2c()
481 		dev_err(&dev->adev->dev, "read from slave 0x%x timed out\n",  in read_i2c()
482 				dev->cli.slave_adr);  in read_i2c()
483 		status = -ETIMEDOUT;  in read_i2c()
492 	for (count = (no_bytes - 2);  in fill_tx_fifo()
494 			(dev->cli.count != 0);  in fill_tx_fifo()
495 			count--) {  in fill_tx_fifo()
496 		/* write to the Tx FIFO */  in fill_tx_fifo()
497 		writeb(*dev->cli.buffer,  in fill_tx_fifo()
498 			dev->virtbase + I2C_TFR);  in fill_tx_fifo()
499 		dev->cli.buffer++;  in fill_tx_fifo()
500 		dev->cli.count--;  in fill_tx_fifo()
501 		dev->cli.xfer_bytes++;  in fill_tx_fifo()
507  * write_i2c() - Write data to I2C client.
521 	writel(mcr, dev->virtbase + I2C_MCR);  in write_i2c()
524 	writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,  in write_i2c()
525 			dev->virtbase + I2C_CR);  in write_i2c()
528 	i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE);  in write_i2c()
530 	init_completion(&dev->xfer_complete);  in write_i2c()
535 	/* Fill the TX FIFO with transmit data */  in write_i2c()
538 	if (dev->cli.count != 0)  in write_i2c()
546 	if (dev->stop || !dev->vendor->has_mtdws)  in write_i2c()
553 	writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,  in write_i2c()
554 			dev->virtbase + I2C_IMSCR);  in write_i2c()
557 		&dev->xfer_complete, dev->adap.timeout);  in write_i2c()
561 		dev_err(&dev->adev->dev, "write to slave 0x%x timed out\n",  in write_i2c()
562 				dev->cli.slave_adr);  in write_i2c()
563 		status = -ETIMEDOUT;  in write_i2c()
570  * nmk_i2c_xfer_one() - transmit a single I2C message
580 		dev->cli.operation = I2C_READ;  in nmk_i2c_xfer_one()
584 		dev->cli.operation = I2C_WRITE;  in nmk_i2c_xfer_one()
588 	if (status || (dev->result)) {  in nmk_i2c_xfer_one()
592 		i2c_sr = readl(dev->virtbase + I2C_SR);  in nmk_i2c_xfer_one()
600 			dev_err(&dev->adev->dev, "%s\n",  in nmk_i2c_xfer_one()
608 		status = status ? status : dev->result;  in nmk_i2c_xfer_one()
615  * nmk_i2c_xfer() - I2C transfer function used by kernel framework
627  *		- a no index is coded as '0',
628  *		- 2byte big endian index is coded as '3'
634  *			msg[0].addr = client->addr;
639  *			msg[1].addr = client->addr;
669 	pm_runtime_get_sync(&dev->adev->dev);  in nmk_i2c_xfer()
677 			dev->cli.slave_adr	= msgs[i].addr;  in nmk_i2c_xfer()
678 			dev->cli.buffer		= msgs[i].buf;  in nmk_i2c_xfer()
679 			dev->cli.count		= msgs[i].len;  in nmk_i2c_xfer()
680 			dev->stop = (i < (num_msgs - 1)) ? 0 : 1;  in nmk_i2c_xfer()
681 			dev->result = 0;  in nmk_i2c_xfer()
691 	pm_runtime_put_sync(&dev->adev->dev);  in nmk_i2c_xfer()
701  * disable_interrupts() - disable the interrupts
708 	writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq),  in disable_interrupts()
709 			dev->virtbase + I2C_IMSCR);  in disable_interrupts()
714  * i2c_irq_handler() - interrupt routine
719  * it handles the major interrupts like Rx & Tx FIFO management
731 	/* load Tx FIFO and Rx FIFO threshold values */  in i2c_irq_handler()
732 	tft = readl(dev->virtbase + I2C_TFTR);  in i2c_irq_handler()
733 	rft = readl(dev->virtbase + I2C_RFTR);  in i2c_irq_handler()
736 	misr = readl(dev->virtbase + I2C_MISR);  in i2c_irq_handler()
744 		if (dev->cli.operation == I2C_READ) {  in i2c_irq_handler()
751 			fill_tx_fifo(dev, (MAX_I2C_FIFO_THRESHOLD - tft));  in i2c_irq_handler()
756 			if (dev->cli.count == 0)  in i2c_irq_handler()
765 	 * greater or equal than the threshold value programmed  in i2c_irq_handler()
769 		for (count = rft; count > 0; count--) {  in i2c_irq_handler()
771 			*dev->cli.buffer = readb(dev->virtbase + I2C_RFR);  in i2c_irq_handler()
772 			dev->cli.buffer++;  in i2c_irq_handler()
774 		dev->cli.count -= rft;  in i2c_irq_handler()
775 		dev->cli.xfer_bytes += rft;  in i2c_irq_handler()
780 		for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) {  in i2c_irq_handler()
781 			*dev->cli.buffer = readb(dev->virtbase + I2C_RFR);  in i2c_irq_handler()
782 			dev->cli.buffer++;  in i2c_irq_handler()
784 		dev->cli.count -= MAX_I2C_FIFO_THRESHOLD;  in i2c_irq_handler()
785 		dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD;  in i2c_irq_handler()
791 		if (dev->cli.operation == I2C_READ) {  in i2c_irq_handler()
792 			while (!(readl(dev->virtbase + I2C_RISR)  in i2c_irq_handler()
794 				if (dev->cli.count == 0)  in i2c_irq_handler()
796 				*dev->cli.buffer =  in i2c_irq_handler()
797 					readb(dev->virtbase + I2C_RFR);  in i2c_irq_handler()
798 				dev->cli.buffer++;  in i2c_irq_handler()
799 				dev->cli.count--;  in i2c_irq_handler()
800 				dev->cli.xfer_bytes++;  in i2c_irq_handler()
807 		if (dev->cli.count) {  in i2c_irq_handler()
808 			dev->result = -EIO;  in i2c_irq_handler()
809 			dev_err(&dev->adev->dev,  in i2c_irq_handler()
811 				dev->cli.count);  in i2c_irq_handler()
814 		complete(&dev->xfer_complete);  in i2c_irq_handler()
820 		dev->result = -EIO;  in i2c_irq_handler()
823 		i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL);  in i2c_irq_handler()
824 		complete(&dev->xfer_complete);  in i2c_irq_handler()
834 		dev->result = -EIO;  in i2c_irq_handler()
836 		if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT)  in i2c_irq_handler()
839 		i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR);  in i2c_irq_handler()
840 		complete(&dev->xfer_complete);  in i2c_irq_handler()
845 	 * Tx FIFO overrun interrupt.  in i2c_irq_handler()
846 	 * This is set when a write operation in Tx FIFO is performed and  in i2c_irq_handler()
847 	 * the Tx FIFO is full.  in i2c_irq_handler()
850 		dev->result = -EIO;  in i2c_irq_handler()
853 		dev_err(&dev->adev->dev, "Tx Fifo Over run\n");  in i2c_irq_handler()
854 		complete(&dev->xfer_complete);  in i2c_irq_handler()
858 	/* unhandled interrupts by this driver - TODO*/  in i2c_irq_handler()
866 		dev_err(&dev->adev->dev, "unhandled Interrupt\n");  in i2c_irq_handler()
869 		dev_err(&dev->adev->dev, "spurious Interrupt..\n");  in i2c_irq_handler()
901 	clk_disable_unprepare(nmk_i2c->clk);  in nmk_i2c_runtime_suspend()
912 	ret = clk_prepare_enable(nmk_i2c->clk);  in nmk_i2c_runtime_resume()
922 		clk_disable_unprepare(nmk_i2c->clk);  in nmk_i2c_runtime_resume()
951 	if (of_property_read_u32(np, "clock-frequency", &nmk->clk_freq))  in nmk_i2c_of_probe()
952 		nmk->clk_freq = I2C_MAX_STANDARD_MODE_FREQ;  in nmk_i2c_of_probe()
955 	if (nmk->clk_freq <= I2C_MAX_STANDARD_MODE_FREQ)  in nmk_i2c_of_probe()
956 		nmk->sm = I2C_FREQ_MODE_STANDARD;  in nmk_i2c_of_probe()
958 		nmk->sm = I2C_FREQ_MODE_FAST;  in nmk_i2c_of_probe()
959 	nmk->tft = 1; /* Tx FIFO threshold */  in nmk_i2c_of_probe()
960 	nmk->rft = 8; /* Rx FIFO threshold */  in nmk_i2c_of_probe()
961 	nmk->timeout = 200; /* Slave response timeout(ms) */  in nmk_i2c_of_probe()
967 	struct device_node *np = adev->dev.of_node;  in nmk_i2c_probe()
970 	struct i2c_vendor_data *vendor = id->data;  in nmk_i2c_probe()
971 	u32 max_fifo_threshold = (vendor->fifodepth / 2) - 1;  in nmk_i2c_probe()
973 	dev = devm_kzalloc(&adev->dev, sizeof(struct nmk_i2c_dev), GFP_KERNEL);  in nmk_i2c_probe()
975 		dev_err(&adev->dev, "cannot allocate memory\n");  in nmk_i2c_probe()
976 		ret = -ENOMEM;  in nmk_i2c_probe()
979 	dev->vendor = vendor;  in nmk_i2c_probe()
980 	dev->adev = adev;  in nmk_i2c_probe()
983 	if (dev->tft > max_fifo_threshold) {  in nmk_i2c_probe()
984 		dev_warn(&adev->dev, "requested TX FIFO threshold %u, adjusted down to %u\n",  in nmk_i2c_probe()
985 			 dev->tft, max_fifo_threshold);  in nmk_i2c_probe()
986 		dev->tft = max_fifo_threshold;  in nmk_i2c_probe()
989 	if (dev->rft > max_fifo_threshold) {  in nmk_i2c_probe()
990 		dev_warn(&adev->dev, "requested RX FIFO threshold %u, adjusted down to %u\n",  in nmk_i2c_probe()
991 			dev->rft, max_fifo_threshold);  in nmk_i2c_probe()
992 		dev->rft = max_fifo_threshold;  in nmk_i2c_probe()
997 	dev->virtbase = devm_ioremap(&adev->dev, adev->res.start,  in nmk_i2c_probe()
998 				resource_size(&adev->res));  in nmk_i2c_probe()
999 	if (!dev->virtbase) {  in nmk_i2c_probe()
1000 		ret = -ENOMEM;  in nmk_i2c_probe()
1004 	dev->irq = adev->irq[0];  in nmk_i2c_probe()
1005 	ret = devm_request_irq(&adev->dev, dev->irq, i2c_irq_handler, 0,  in nmk_i2c_probe()
1008 		dev_err(&adev->dev, "cannot claim the irq %d\n", dev->irq);  in nmk_i2c_probe()
1012 	dev->clk = devm_clk_get(&adev->dev, NULL);  in nmk_i2c_probe()
1013 	if (IS_ERR(dev->clk)) {  in nmk_i2c_probe()
1014 		dev_err(&adev->dev, "could not get i2c clock\n");  in nmk_i2c_probe()
1015 		ret = PTR_ERR(dev->clk);  in nmk_i2c_probe()
1019 	ret = clk_prepare_enable(dev->clk);  in nmk_i2c_probe()
1021 		dev_err(&adev->dev, "can't prepare_enable clock\n");  in nmk_i2c_probe()
1027 	adap = &dev->adap;  in nmk_i2c_probe()
1028 	adap->dev.of_node = np;  in nmk_i2c_probe()
1029 	adap->dev.parent = &adev->dev;  in nmk_i2c_probe()
1030 	adap->owner = THIS_MODULE;  in nmk_i2c_probe()
1031 	adap->class = I2C_CLASS_DEPRECATED;  in nmk_i2c_probe()
1032 	adap->algo = &nmk_i2c_algo;  in nmk_i2c_probe()
1033 	adap->timeout = msecs_to_jiffies(dev->timeout);  in nmk_i2c_probe()
1034 	snprintf(adap->name, sizeof(adap->name),  in nmk_i2c_probe()
1035 		 "Nomadik I2C at %pR", &adev->res);  in nmk_i2c_probe()
1039 	dev_info(&adev->dev,  in nmk_i2c_probe()
1041 		 adap->name, dev->virtbase);  in nmk_i2c_probe()
1047 	pm_runtime_put(&adev->dev);  in nmk_i2c_probe()
1052 	clk_disable_unprepare(dev->clk);  in nmk_i2c_probe()
1060 	struct resource *res = &adev->res;  in nmk_i2c_remove()
1063 	i2c_del_adapter(&dev->adap);  in nmk_i2c_remove()
1068 	i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE);  in nmk_i2c_remove()
1069 	clk_disable_unprepare(dev->clk);  in nmk_i2c_remove()
1070 	release_mem_region(res->start, resource_size(res));  in nmk_i2c_remove()